Apparatus and method for leadless packaging of semiconductor devices
First Claim
1. A semiconductor package, comprising:
- a first semiconductor chip having an upper surface;
a second semiconductor chip having an upper surface and an opposing lower surface, the lower surface of the second chip being positioned on the upper surface of the first chip to define an exposed portion of the upper surface of the first chip, the first chip further including a first plurality of bond pads disposed on the exposed portion, and the second chip further including a second plurality of bond pads disposed on the upper surface of the second chip;
a plurality of interconnections that extend from the first plurality of bond pads to the second plurality of bond pads, the interconnections being disposed on selected portions of the first and second chips to electrically couple the first and second chips; and
a plurality of castellations disposed on selected portions of the first chip that extend outwardly from the first plurality of bond pads to form leadless input/output locations for the package.
7 Assignments
0 Petitions
Accused Products
Abstract
The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.
-
Citations
80 Claims
-
1. A semiconductor package, comprising:
-
a first semiconductor chip having an upper surface;
a second semiconductor chip having an upper surface and an opposing lower surface, the lower surface of the second chip being positioned on the upper surface of the first chip to define an exposed portion of the upper surface of the first chip, the first chip further including a first plurality of bond pads disposed on the exposed portion, and the second chip further including a second plurality of bond pads disposed on the upper surface of the second chip;
a plurality of interconnections that extend from the first plurality of bond pads to the second plurality of bond pads, the interconnections being disposed on selected portions of the first and second chips to electrically couple the first and second chips; and
a plurality of castellations disposed on selected portions of the first chip that extend outwardly from the first plurality of bond pads to form leadless input/output locations for the package. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
-
-
26. A semiconductor package, comprising:
-
a first semiconductor chip having an upper surface;
a second semiconductor chip having an upper surface and an opposing lower surface, the lower surface of the second chip being positioned on the upper surface of the first chip to define an exposed portion of the upper surface of the first chip, the first chip further including a first plurality of bond pads disposed on the exposed portion, and the second chip further including a second plurality of bond pads disposed on the upper surface of the second chip;
a plurality of wire bond elements that extend from the first plurality of bond pads to the second plurality of bond pads to electrically couple the first and second chips; and
a plurality of castellations disposed on selected portions of the first chip that extend outwardly from the first plurality of bond pads to form leadless input/output locations for the package. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
-
-
44. A package for a photosensitive device capable of sensing incident light, comprising:
-
a semiconductor chip having an upper surface that supports the photosensitive device, the chip having a plurality of bond pads exposed at the upper surface that are coupled to the device;
at least one optical layer disposed on the photosensitive device; and
a plurality of castellations disposed on selected portions of the chip that extend outwardly from the bond pads to form a plurality of leadless input/output locations for the package. - View Dependent Claims (45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56)
-
-
57. A method for forming a leadless, interconnected semiconductor package, comprising:
-
disposing a second semiconductor chip onto a first semiconductor chip, each chip having a plurality of exposed bond pads;
forming a plurality of interconnections that extend from bond pads on the first chip to corresponding bond pads on the second chip; and
forming a plurality of castellations that extend from the bond pads on the first chip. - View Dependent Claims (58, 59, 60, 61, 62, 63)
-
-
64. A method for fabricating a plurality of vertically stacked, interconnected and leadless semiconductor packages, comprising:
-
supporting a substrate having a plurality of first semiconductor chips formed therein, the first chips having a first plurality of bond pads exposed at an upper surface of the substrate;
positioning a plurality of second semiconductor chips onto the substrate, each second chip being positioned on a single first chip and having a second plurality of bond pads;
depositing a plurality of interconnections onto the first chips and the second chips that extend between corresponding bond pads on the first and second chips;
singulating the substrate to obtain a plurality of separated semiconductor packages; and
depositing a plurality of castellations to the first chips that extend outwardly from the first plurality of bond pads. - View Dependent Claims (65, 66, 67, 68, 69, 70, 71, 72)
-
-
73. A method for fabricating a plurality of photosensing packages, comprising:
-
supporting a substrate having a plurality of photosensitive devices formed on an upper surface of the substrate, each photosensitive device having a plurality of bond pads disposed on the upper surface;
disposing at least one optical layer onto the photosensitive device;
forming a plurality of drains in the upper surface of the substrate that are positioned between adjacent photosensitive devices and project at least partially into the substrate;
thinning the substrate at a lower surface that opposes the upper surface to expose the plurality of drains; and
depositing a plurality of castellations onto the packages that extend outwardly from the plurality of bond pads. - View Dependent Claims (74, 75, 76, 77, 78, 79, 80)
-
Specification