Transflective liquid crystal display device and fabricating method thereof

• US 20030071944A1
• Filed: 10/10/2002
• Published: 04/17/2003
• Est. Priority Date: 10/11/2001
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Baek, Heum-Il
• Granted Patent: US 7,184,113 B2
• Time in Patent Office: Days
• US Class Current: 349/113
• CPC Class Codes: G02F 1/133553 Reflecting elements associated to illuminating devices G02F1/133605
• CPC Class Codes: G02F 1/133555 Transflectors
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13685 Top gates

Abstract

A fabricating method of an array substrate for a transflective liquid crystal display device includes: sequentially depositing a first metal layer and an impurity-doped amorphous silicon layer on a substrate and etching the first metal layer and the impurity-doped amorphous silicon layer through a first mask process to form source and drain electrodes, a data line and an ohmic contact layer. An amorphous silicon layer, a first insulating layer and a second metal layer are sequentially deposited on the source and drain electrodes, the data line and the ohmic contact layer and etching the amorphous silicon layer, the first insulating layer and the second metal layer through a second mask process to form a gate electrode, a gate line and an active layer, the gate line defining a pixel region with the data line. A second insulating layer is formed on the gate electrode and the gate line. A reflective plate is formed on the second insulating layer at the pixel region through a third mask process, the reflective plate having a transmissive hole. A third insulating layer is deposited on the reflective plate and etching the third insulating layer through a fourth mask process to form a drain contact hole exposing the drain electrode and a transmissive groove corresponding to the transmissive hole. A pixel electrode is formed on the third insulating layer through a fifth mask process, the pixel electrode being connected to the drain electrode through the drain contact hole.

Claims

1. An array substrate for a transflective liquid crystal display device, comprising:

a substrate;

a data line and a gate line on the substrate, the data line and the gate line defining a pixel region;

a thin film transistor connected to the data line and the gate line, the thin film transistor including source and drain electrodes, an ohmic contact layer on the source and drain electrodes, an active layer and a gate electrode over the active layer;

a reflective plate at the pixel region, the reflective plate having a transmissive hole; and

a pixel electrode over the reflective plate, the pixel electrode being connected to the drain electrode.

2. The substrate according to claim 1, further comprising a first insulating layer between the active layer and the gate electrode.

3. The substrate according to claim 2, further comprising a second insulating layer covering the thin film transistor, wherein the reflective plate is formed on the second insulating layer.

4. The substrate according to claim 3, further comprising a third insulating layer on the reflective plate, wherein the third insulating layer has a drain contact hole and a transmissive groove through the second insulating layer, wherein the pixel electrode is formed on the third insulating layer and connected to the drain electrode through the drain contact hole.

5. A fabricating method of an array substrate for a transflective liquid crystal display device, comprising:

sequentially depositing a first metal layer and an impurity-doped amorphous silicon layer on a substrate;

etching the first metal layer and the impurity-doped amorphous silicon layer through a first mask process to form source and drain electrodes, a data line and an ohmic contact layer;

sequentially depositing an amorphous silicon layer, a first insulating layer and a second metal layer on the source and drain electrodes, the data line and the ohmic contact layer;

etching the amorphous silicon layer, the first insulating layer and the second metal layer through a second mask process to form a gate electrode, a gate line and an active layer, the gate line defining a pixel region with the data line;

forming a second insulating layer on the gate electrode and the gate line;

forming a reflective plate on the second insulating layer at the pixel region through a third mask process, the reflective plate having a transmissive hole;

depositing a third insulating layer on the reflective plate;

etching the third insulating layer through a fourth mask process to form a drain contact hole exposing the drain electrode and a transmissive groove corresponding to the transmissive hole; and

forming a pixel electrode on the third insulating layer through a fifth mask process, the pixel electrode being connected to the drain electrode through the drain contact hole.

6. The method according to claim 5, wherein the first insulating layer is formed between the active layer and the gate electrode.

7. The method according to claim 5, wherein etching the first metal layer and the impurity-doped amorphous silicon layer through a first mask process further forms a data pad at one end of the data line.

8. The method according to claim 7, wherein etching the amorphous silicon layer, the first insulating layer and the second metal layer through a second mask process further forms a gate pad at one end of the gate line.

9. The method according to claim 8, wherein etching the third insulating layer through a fourth mask process further forms a data pad contact hole and a gate pad contact hole exposing the data pad and the gate pad, respectively.

10. The method according to claim 9, wherein forming a pixel electrode further forms a data pad terminal and a gate pad terminal connected to the data pad and the gate pad, respectively.

11. The method according to claim 5, wherein etching the impurity-doped amorphous silicon is performed by a dry etching method and etching the first metal layer is performed by a wet etching method.

12. The method according to claim 5, wherein the reflective plate has one of a conductive metal group including aluminum (A1) and aluminum (A1) alloy.

13. The method according to claim 5, wherein the pixel electrode has one of a transparent conductive metal group including indium-tin-oxide (ITO) and indium-zinc-oxide (IZO).

14. An array substrate for a transflective liquid crystal display device, comprising:

a substrate;

a data line and a gate line on the substrate, the data line and the gate line defining a pixel region;

a thin film transistor connected to the data line and the gate line, the thin film transistor including source and drain electrodes, an ohmic contact layer on the source and drain electrodes, an active layer and a gate electrode over the active layer;

a reflective plate at the pixel region, the reflective plate having a transmissive hole and an unevenness;

a plurality of convex patterns under the reflective plate; and

a pixel electrode over the reflective plate, the pixel electrode being connected to the drain electrode.

15. The substrate according to claim 14, wherein the plurality of convex patterns corresponds to the unevenness.

16. The substrate according to claim 14, further comprising a first insulating layer between the active layer and the gate electrode.

17. The substrate according to claim 16, further comprising a second insulating layer covering the thin film transistor, wherein the reflective plate is formed on the second insulating layer.

18. The substrate according to claim 17, further comprising a third insulating layer on the reflective plate, wherein the third insulating layer has a drain contact hole and a transmissive groove through the second insulating layer, wherein the pixel electrode is formed on the third insulating layer and connected to the drain electrode through the drain contact hole.

19. The substrate according to claim 18, wherein the plurality of convex patterns has the same structure as a multi-layer including the active layer, the first insulating layer and the gate electrode.

20. A fabricating method of an array substrate for a transflective liquid crystal display device, comprising:

sequentially depositing a first metal layer and an impurity-doped amorphous silicon layer on a substrate;

etching the first metal layer and the impurity-doped amorphous silicon layer through a first mask process to form source and drain electrodes, a data line and an ohmic contact layer;

sequentially depositing an amorphous silicon layer, a first insulating layer and a second metal layer on the source and drain electrodes, the data line and the ohmic contact layer;

etching the amorphous silicon layer, the first insulating layer and the second metal layer through a second mask process to form a gate electrode, a gate line, an active layer and a plurality of convex patterns, the gate line defining a pixel region with the data line;

forming a second insulating layer on the gate electrode, the gate line and the plurality of convex patterns;

forming a reflective plate on the second insulating layer at the pixel region through a third mask process, the reflective plate having a transmissive hole and an unevenness;

depositing a third insulating layer on the reflective plate;

etching the third insulating layer through a fourth mask process to form a drain contact hole exposing the drain electrode and a transmissive groove corresponding to the transmissive hole; and

forming a pixel electrode on the third insulating layer through a fifth mask process, the pixel electrode being connected to the drain electrode through the drain contact hole.

21. The method according to claim 20, wherein the first insulating layer is formed between the active layer and the gate electrode.

22. The method according to claim 20, wherein the plurality of convex patterns corresponds to the unevenness.

23. The substrate according to claim 20, wherein the plurality of convex patterns includes the amorphous silicon layer, the first insulating layer and the second metal layer.

24. The method according to claim 20, wherein etching the first metal layer and the impurity-doped amorphous silicon layer through a first mask process further forms a data pad at one end of the data line.

25. The method according to claim 24, wherein etching the amorphous silicon layer, the first insulating layer and the second metal layer through a second mask process further forms a gate pad at one end of the gate line.

26. The method according to claim 25, wherein etching the third insulating layer through a fourth mask process further forms a data pad contact hole and a gate pad contact hole exposing the data pad and the gate pad, respectively.

27. The method according to claim 26, wherein forming a pixel electrode further forms a data pad terminal and a gate pad terminal connected to the data pad and the gate pad, respectively.

28. The method according to claim 20, wherein etching the impurity-doped amorphous silicon is performed by a dry etching method and etching the first metal layer is performed by a wet etching method.

29. The method according to claim 20, wherein the reflective plate has one of a conductive metal group including aluminum (A1) and aluminum (A1) alloy.

30. The method according to claim 20, wherein the pixel electrode has one of a transparent conductive metal group including indium-tin-oxide (ITO) and indium-zincoxide (IZO).