Programming of nonvolatile memory cells

• US 20030072192A1
• Filed: 05/28/2002
• Published: 04/17/2003
• Est. Priority Date: 05/04/2000
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Maayan, Eduardo, Bloom, Ilan, Cohen, Zeev, Finzi, David
• Granted Patent: US 6,829,172 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming

Abstract

A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.

Claims

1. A method for programming an NROM cell, the method comprising the steps of:

applying a drain, a source and a gate voltage to said cell;

verifying a programmed or a non-programmed state of said cell; and

if said cell is in said non-programmed state;

increasing said drain voltage; and

maintaining said gate voltage at a constant level during at least a part of said step of increasing, and

repeating said steps of applying, verifying, increasing and maintaining until said cell reaches said programmed state.

3. A method according to claim 1 or 2, wherein said step of increasing includes the step of stepping said drain voltage.

4. A method according to claim 3, wherein said step of stepping includes the step of executing non-linear steps.

5. A method according to claim 3, wherein said step of stepping includes the step of executing equal amplitude steps.

6. A method according to claim 5, wherein each equal amplitude step produces an equivalent step in a threshold voltage of said NROM cell.

7. A method according to claim 3, wherein said step of stepping includes the step of executing steps of equal time duration.

8. A method according to claim 3, wherein said step of stepping includes the step of executing steps of unequal time duration.

9. A method according to claim 1 or 2 and further comprising the step of dialing in an initial drain voltage.

10. A method according to claim 1 or 2, wherein said step of maintaining includes the step of changing said gate voltage at least once.

11. A method according to claim 1 or 2, wherein said step of maintaining includes the step of maintaining said gate voltage constant throughout said step of increasing.

12. A method according to claim 1 or 2, wherein said step of applying includes the step of applying a maximum gate voltage to said gate.

13. A method according to claim 1 or 2, wherein said step of applying includes the step of beginning said drain voltage at a low voltage level.

14. A method according to claim 1 or 2, wherein said step of applying includes the step of stopping said drain voltage at a voltage level slightly above a saturated threshold voltage level of said cell.

15. A method according to claim 1 or 2, wherein said step of repeating occurs 3-7 times.

2. A method for controlling the programming time of an NROM cell, the method comprising the steps of:

applying a drain, a source and a gate voltage to said cell;

verifying a programmed or a non-programmed state of said cell; and

if said cell is in said non-programmed state;

increasing said drain voltage; and

maintaining said gate voltage at a constant level during at least a part of said step of increasing, and

repeating said steps of applying, verifying, increasing and maintaining until said cell reaches said programmed state.

16. A method for programming of an NROM cell having two diffusion areas and a channel therebetween, the method comprising the steps of:

controlling a voltage across said channel during programming;

verifying a programmed or a non-programmed state of said cell; and

repeating said steps of controlling and verifying until said cell reaches said programmed state.

17. A method for programming of an NROM cell having two diffusion areas and a channel therebetween, the method comprising the steps of:

maintaining a constant current in said channel during programming;

verifying a programmed or a non-programmed state of said cell; and

repeating said steps of controlling and verifying until said cell reaches said programmed state.

18. A method for confining charge within a predefined region of a retention layer of an NROM cell having a gate, the method comprising the steps, during programming, of;

applying an incrementally increasing drain voltage to a diffusion area acting as a drain of said cell; and

maintaining a constant gate voltage on said gate during at least a part of said step of applying;

verifying a programmed or a non-programmed state of said cell; and

if said cell is in said non-programmed state, repeating said steps of applying, maintaining and verifying until said cell reaches said programmed state.

22. A method according to any one of claims 18-21, wherein said step of applying begins at a low voltage level.

23. A method according to any one of claims 18-21, wherein said step of repeating includes the step of stopping at a voltage level slightly above a saturated threshold voltage level of said cell.

24. A method according to any one of claims 18-21 and further comprising the step of applying a maximum gate voltage to said gate of said cell.

25. A method according to any one of claims 18-20, wherein said predefined region is close to said diffusion area.

27. A method according to any one of claims 18-21, wherein said step of applying includes the step of stepping said drain voltage.

28. A method according to claim 27, wherein said step of stepping includes the step of executing non-linear steps.

29. A method according to claim 27, wherein said step of stepping includes the step of executing equal amplitude steps.

30. A method according to claim 29, wherein each equal amplitude step produces an equivalent step in a threshold voltage of said NROM cell.

31. A method according to claim 27, wherein said step of stepping includes the step of executing steps of equal time duration.

32. A method according to claim 27, wherein said step of stepping includes the step of executing steps of unequal time duration.

33. A method according to any one of claims 18-21 and further comprising the step of dialing in an initial drain voltage.

34. A method according to any one of claims 18-21, wherein said step of maintaining includes the step of changing said gate voltage at least once.

35. A method according to any one of claims 18-21, wherein said step of maintaining includes the step of maintaining said gate voltage constant throughout said step of applying.

19. A method for retaining charge in an NROM cell having a gate and a retention layer, the method comprising the steps of:

confining said charge within a predefined region of said retention layer of said cell by;

applying an incrementally increasing drain voltage to a diffusion area acting as a drain of said cell; and

maintaining a constant gate voltage on said gate during at least a part of said step of applying;

verifying a programmed or a non-programmed state of said cell; and

if said cell is in said non-programmed state, repeating said steps of confining and verifying until said cell reaches said programmed state.

20. A method for retaining charge in an NROM cell having a gate and a retention layer, the method comprising the steps of;

providing a compact spatial charge distribution within a predefined region of said retention layer of said cell by;

applying an incrementally increasing drain voltage to a diffusion area acting as a drain of said cell; and

maintaining a constant gate voltage on said gate during at least a part of said step of applying;

verifying a programmed or a non-programmed state of said cell; and

if said cell is in said non-programmed state, repeating said steps of providing and verifying until said cell reaches said programmed state.

36. An NROM cell having charge retained by the method of claim 20 or 21.

37. A charge distribution as created by the method of claim 20 or 21.

38. An NROM cell comprising:

a retention element;

two diffusion areas, one on either side of said retention element; and

at least one compact spatial charge distribution within said retention element and near at least one of said diffusion areas, as created by the method of claim 20 or 21.

39. An NROM cell according to claim 38 wherein said charge distribution is removable in generally its entirety.

40. An NROM cell according to claim 39 wherein said charge distribution is removable in generally its entirety.

21. A method for retaining the separation distance between two charge regions in an NROM cell having a gate and two diffusion areas, the method comprising the steps of, for each charge region:

applying an incrementally increasing drain voltage to the diffusion area closest to said charge region; and

maintaining a constant gate voltage on said gate during at least a part of said step of applying;

verifying a programmed or a non-programmed state of said cell; and

if said cell is in said non-programmed state, repeating said steps of applying, maintaining and verifying until said cell reaches said programmed state.

26. A method according to claim 21, wherein said charge regions are close to one of said two diffusion areas.

41. A method for programming an NROM cell, the method comprising the steps, during programming, of:

applying a drain, a source and a gate voltage; and

while keeping said gate voltage at at least one constant level, increasing said drain voltage until said cell reaches saturation.

42. A method for programming an NROM cell having two diffusion areas and a channel therebetween, the method comprising the step of controlling a voltage across said channel during programming, until said cell reaches saturation.

43. A method for programming an NROM cell having two diffusion areas and a channel therebetween, the method comprising the step of maintaining a constant current in said channel during programming, until said cell reaches saturation.

44. A method for controlling a change in the threshold voltage of an NROM cell wherein the cell receives a drain, a source and a gate voltage, the method comprising the step, during programming, of varying said drain voltage while keeping said gate voltage at at least one constant level.

45. A method for controlling the programming time of an NROM cell, the method comprising the steps of:

applying a drain, a source and a gate voltage; and

while keeping said gate voltage at at least one constant level, incrementally increasing said drain voltage during programming, until said cell reaches saturation.

46. A method for programming an array of NROM cells having varying programming speeds, the array having bit lines and word lines, the method comprising the steps of:

providing a gate voltage to one of said word lines;

providing a source voltage to a first bit line and a drain voltage to a second bit line; and

varying said drain voltage while keeping said gate voltage at a constant level until said array of cells reach saturation.

47. A method for retaining the separation distance between two charge regions in an NROM cell, the NROM cell having a gate and two diffusion areas, the method comprising the step of, while applying at least one constant gate voltage to said gate, for each charge region, applying an incrementally increasing bit line voltage to the diffusion area closest to said charge region, until said cell reaches saturation.

48. A method for retaining charge in an NROM cell having a gate and a retention layer, the method comprising the step of providing a compact spatial charge distribution within a predefined region of said retention layer of said cell by applying an incrementally increasing bit line voltage to a diffusion area acting as a drain of said cell, while applying at least one constant gate voltage to said gate, until said cell reaches saturation.