Trench-gate semiconductor devices and their manufacture

• US 20030073289A1
• Filed: 09/18/2002
• Published: 04/17/2003
• Est. Priority Date: 10/11/2001
• Status: Abandoned Application

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Curry, Steven J., Peake, Steven T.
• Application Number:
  US10/246,171
• Publication Number:
  US 20030073289A1
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Trench-gate field-effect semiconductor devices, for example cellular power MOSFETs with compact geometries, comprise a semiconductor body (10) into which the trench-gate (11) extends from a surface-adjacent source region (13) through a channel-accommodating region (15) of opposite conductivity type (p) and into an underlying drain drift region (14). This invention provides the gate trench (20) with a width (w) that is smaller than its depth (d) and that tapers increasingly towards the bottom of the gate trench (20) to reduce the width (w) of the trench-gate (11) at a greater rate in the drain drift region (14) than in the channel-accommodating region (15).

Claims

1. A trench-gate field-effect semiconductor device comprising a semiconductor body into which the trench-gate extends from a surface-adjacent source region of a first conductivity type through a channel-accommodating region of a second conductivity type and into an underlying drain drift region of the first conductivity type, wherein the gate trench has a width that is smaller than its depth in the semiconductor body and that tapers increasingly towards the bottom of the gate trench to reduce the width of the trench-gate at a greater rate in the drain drift region than in the channel-accommodating region.

2. A device according to claim 1, wherein the width of the gate trench tapers in the drain drift region to less than 0.7 of its initial width in the channel-accommodating region.

3. A device according to claim 1 or claim 2, wherein the trench-gate is capacitively coupled to the channel-accommodating region across a gate dielectric layer, and the gate dielectric layer lines the side-walls of the gate trench in the drain drift region as well as in the channel-accommodating region.

4. A device according to claim 3, wherein the gate dielectric layer is of substantially uniform thickness along the side-walls of the trench, and the width reduction of the gate trench in the drain drift region reduces gate-drain capacitance as compared with a gate trench of uniform width.

5. A device according to any one of the preceding claims, wherein the rate of width reduction of the trench-gate over a lower one-third (for example a lower 0.5 μ

m) of the depth of the trench-gate is almost three times that over an upper two-thirds (for example an upper 1 μ

m) of the depth of the trench-gate.

6. A device according to claim 5, wherein the trench-gate has a depth (for example of 1.5 μ

m) that is more than six times larger than its width in the channel-accommodating region.

7. A device according to claim 5 or claim 6, wherein there is substantially no taper of the trench-gate over at least most of the depth of the channel-accommodating region.

13. A device according to any one of claims 1 to 7, wherein additional device features resulting from the use of method claims 8 to 12 are also included.

8. A method of manufacturing a trench-gate field-effect semiconductor device, in which the trench-gate extends from a surface-adjacent source region of a first conductivity type through a channel-accommodating region of a second conductivity type and into an underlying drain drift region of the first conductivity type, and wherein the method includes the following sequence of steps:

(a) providing a semiconductor body having an upper first portion where the channel-accommodating region is present or is to be provided and having a lower second portion that is to provide the drain drift region,

(b) forming on the semiconductor body a mask having a window defining the location and width of a trench to be etched into the semiconductor body for accommodating the trench-gate,

(c) etching the trench to a depth that is greater than its width and that extends so deeply into the semiconductor body that the width of the trench reduces in size towards the bottom of the trench, with the rate of the width reduction of the trench being greater in the lower second portion of the semiconductor body than in the upper first portion of the semiconductor body, and

(d) providing the trench-gate in the trench.

9. A method according to claim 8, wherein the channel-accommodating region is provided in the semiconductor body by introducing dopant of the said opposite conductivity type into the upper first portion of the semiconductor body after the step (d) when the dopant diffusion rate in the lower second portion is slowed along the increasingly-tapered side-wall portions of the trench in the lower second portion.

10. A method according to claim 8 or claim 9, wherein between steps (c) and (d) the trench is lined at least at its side-walls with a silicon dioxide layer that provides at least part of a gate dielectric layer for capacitively coupling the trench-gate to the channel-accommodating region.

11. A method according to any one of claims 8 to 10, wherein the step (b) includes forming the trench-etch window as a narrowed window by providing side-wall extensions at the side-walls of a wider window first formed in the mask.

12. A method according to any one of claims 8 to 11, wherein the additional features of device claims 2 to 7 are also provided.