Configurable asic memory bist controller employing multiple state machines
First Claim
1. A built-in self-test controller, comprising:
- a plurality of alternative memory built-in self-test state machines; and
a memory built-in self-test engine operating a predetermined one of the memory built-in self-test state machines.
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Abstract
A method and apparatus for performing a memory built-in self-test for an integrated circuit are disclosed. The technique includes a memory built-in self-test controller including a plurality of alternative memory built-in self-test state machines and a memory built-in self-test engine operating a predetermined one of the memory built-in self-test state machines. It also includes a method for performing a built-in self-test on an integrated circuit device. The method includes externally resetting a predetermined one of a plurality of memory state machines in a memory built-in self-test controller; performing a memory built-in self-test utilizing the reset memory state machine; and obtaining the results of the performed memory built-in self-test.
38 Citations
36 Claims
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1. A built-in self-test controller, comprising:
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a plurality of alternative memory built-in self-test state machines; and
a memory built-in self-test engine operating a predetermined one of the memory built-in self-test state machines. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A built-in self-test controller, comprising:
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means for implementing a plurality of states in a plurality of sets in a memory built-in self-test; and
means for operating a predetermined one of the sets in the memory built-in self-test. - View Dependent Claims (8, 9, 10)
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11. An integrated circuit device, comprising:
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a plurality of memory components;
a testing interface; and
a built-in self-test controller controlled through the testing interface, comprising;
a plurality of alternative memory built-in self-test state machines; and
a memory built-in self-test engine operating a predetermined one of the memory built-in self-test state machines. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. An integrated circuit device, comprising:
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a plurality of memory components;
a testing interface; and
a built-in self-test controller controlled through the testing interface, comprising;
means for implementing a plurality of states in a plurality of sets in a memory built-in self-test; and
means for operating a predetermined one of the sets in the memory built-in self-test. - View Dependent Claims (20, 21, 22, 23, 24)
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25. A method for performing a built-in self-test on an integrated circuit device, comprising:
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externally resetting a predetermined one of a plurality of memory state machines in a memory built-in self-test controller;
performing a memory built-in self-test utilizing the reset memory state machine; and
obtaining the results of the performed memory built-in self-test. - View Dependent Claims (26, 27, 28, 29)
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30. A method for testing an integrated circuit device, comprising:
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interfacing the integrated circuit device with a tester;
externally resetting a built-in self-test controller, including;
externally resetting a predetermined one of a plurality of memory state machines;
performing a memory built-in self-test from the built-in self-test controller;
obtaining the results of the performed memory built-in self-test. - View Dependent Claims (31, 32, 33, 34, 35, 36)
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Specification