Convolutional encoder and method of operation

• US 20030074627A1
• Filed: 09/26/2002
• Published: 04/17/2003
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: MacDougall, Scott
• Granted Patent: US 7,287,210 B2
• Time in Patent Office: Days
• US Class Current: 714/786
• CPC Class Codes: H03M 13/23 using convolutional codes, e.g. unit memory codes

Abstract

A method of convolutionally encoding (700) a data stream includes inputting a first block of two or more bits (710) in parallel into a shift register. A number of intermediate calculations (715) are performed in parallel using a number of respective delayed shift register outputs; and said number of intermediate calculations (715) are output (725) to form a convolutionally encoded sequence.

A convolutional encoder, communication unit and communication system adapted to implement the convolutional encoder are also described.

Setting up a register (of individual bits stored in words), which is longer than the constraint length means that a relatively large number of input bits can be read from memory only once, thus avoiding many independent moves of operands to and from memory. Since the register is longer than the constraint length, the register need only be shifted once for every ‘a+1’ input bits, rather than once for each bit.

Claims

1. A method of convolutionally encoding a data stream characterised by the following steps:

inputting a first block of two or more bits in parallel into a shift register;

performing a number of intermediate calculations in parallel using a number of respective delayed shift register outputs; and

outputting said number of intermediate calculations to form a convolutionally encoded sequence.

2. The method of convolutionally encoding a data stream according to claim 1, the method further characterised by the following steps:

inputting a second block of two or more bits in parallel into said shift register, when said intermediate calculations have been performed and if more data is provided; and

performing further intermediate calculations on a number of respective shift register outputs.

3. The method of convolutionally encoding a data stream according to claim 2, wherein the step of inputting a second block includes the steps of:

shifting register bit values by said two or more bits per cycle; and

reading two or more new input bits into said shift register.

4. The method of convolutionally encoding a data stream according to any claim 1, the method further characterised by the following step:

utilising one or more result of said number of intermediate calculations in one or more data registers to perform further calculations prior to storing a final convolutionally encoded output in memory.

5. The method of convolutionally encoding a data stream according to claim 1, the method further characterised by the step of:

configuring or selecting said shift register such that said number of bits input into said shift register in parallel is longer than a constraint length of the convolutionally encoded sequence to be output.

6. The method of convolutionally encoding a data stream according to claim 1, the method further characterised by the step of:

inputting said number of bits into said shift register as individual words.

7. The method of convolutionally encoding a data stream according to claim 1, the method further characterised by the step of:

sharing one or more result of said number of intermediate calculations, for each set of parallel input bits, across one or more sets of outputs.

8. A convolutional encoder adapted to perform the method steps of claim 1.

9. A communication unit adapted to perform the convolutional encoding method steps of claim 1.

10. A communication system adapted to facilitate the convolutional encoding method steps of claim 1.

11. A convolutional encoder for convolutionally encoding a data stream the convolutional encoder comprising:

one or more input ports;

a shift register operably coupled to said one or more input ports for receiving said data stream;

calculation means, operably coupled to said shift register to perform logical calculations on delayed outputs from said shift register; and

one or more output ports, operably coupled to said calculation means, to output a convolutionally encoded data stream;

the convolutional encoder characterised by;

said shift register receiving a first block of two or more bits of said data stream in parallel; and

said calculation means performing a number of intermediate calculations in parallel using a number of respective delayed shift register outputs.

12. The convolutional encoder according to claim 11, further characterised by said calculation means performing said intermediate calculations in a series of pre-determined stages.

13. The convolutional encoder according to claim 11, further characterised by said shift register receiving a second block of two or more bits of said data stream in parallel when said intermediate calculations have been performed and if more data is provided.

14. The convolutional encoder according to claim 11, further characterised by said second block of bits being input to said shift register by shifting register bit values by said two or more bits per cycle;

followed by inputting two or more new input bits from said data stream into said shift register.

15. The convolutional encoder according to claim 11, further characterised by said number of bits input into said shift register in parallel being longer than a constraint length of the convolutionally encoded sequence to be output.

16. The convolutional encoder according to claim 11, further characterised by said shift register receiving said number of bits in parallel as individual words.

17. The convolutional encoder according to claim 11, further characterised by said calculation means sharing one or more result of said number of intermediate calculations, for each set of parallel input bits, across one or more sets of outputs.

18. A communication unit comprising the convolutional encoder of claim 11.

19. A communication system comprising the communication unit of claim 18.