Compiler-directed speculative approach to resolve performance-degrading long latency events in an application

• US 20030074653A1
• Filed: 09/28/2001
• Published: 04/17/2003
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wu, Youfeng, Ju, Dz-Ching
• Granted Patent: US 6,959,435 B2
• Time in Patent Office: Days
• US Class Current: 717/154
• CPC Class Codes: G06F 8/4451 Avoiding pipeline stalls

Abstract

A compiler-directed speculative approach to resolve performance-degrading long latency events in an application is described. One or more performance-degrading instructions are identified from multiple instructions to be executed in a program. A set of instructions prefetching the performance-degrading instruction is defined within the program. Finally, at least one speculative bit of each instruction of the identified set of instructions is marked to indicate a predetermined execution of the instruction.

Claims

1. A method comprising:

identifying at least one performance-degrading instruction from a plurality of instructions to be executed in a program;

defining a set of instructions within said program to prefetch said at least one performance-degrading instruction; and

marking at least one speculative bit of each instruction of said set of instructions to indicate a predetermined execution of said each instruction.

2. The method according to claim 1, further comprising:

inserting a launch point to launch said predetermined execution; and

inserting a termination point to terminate said predetermined execution.

3. The method according to claim 1, wherein said identifying further comprises:

monitoring execution of said plurality of instructions; and

detecting said at least one performance-degrading instruction.

4. The method according to claim 1, wherein said defining further comprises:

reducing a size of said set of instructions based on speculation and prediction techniques.

5. The method according to claim 4, wherein said reducing further comprises:

determining whether a first instruction of said set of instructions is aliased with a second instruction within said set of instructions; and

removing said first instruction and adjacent instructions related to said first instruction from said set, if said first instruction is not aliased with said second instruction.

6. The method according to claim 2, wherein inserting said launch point further comprises:

determining a first instruction of said set of instructions;

determining whether variables of said set of instructions are ready for execution; and

determining whether a latency value from said launch point to said performance-degrading instruction is greater than a total latency value of said set of instructions including a miss latency of said performance-degrading instruction.

7. The method according to claim 2, wherein inserting said termination point further comprises:

marking said termination point subsequent to said performance-grading instruction.

8. A system comprising:

means for identifying at least one performance-degrading instruction from a plurality of instructions to be executed in a program;

means for defining a set of instructions within said program to prefetch said at least one performance-degrading instruction; and

means for marking at least one speculative bit of each instruction of said set of instructions to indicate a predetermined execution of said each instruction.

9. The system according to claim 8, further comprising:

means for inserting a launch point to launch said predetermined execution; and

means for inserting a termination point to terminate said predetermined execution.

10. The system according to claim 8, further comprising:

means for monitoring execution of said plurality of instructions; and

means for detecting said at least one performance-degrading instruction.

11. The system according to claim 8, further comprising:

means for reducing a size of said set of instructions based on speculation and prediction techniques.

12. The system according to claim 11, further comprising:

means for determining whether a first instruction of said set of instructions is aliased with a second instruction within said set of instructions; and

means for removing said first instruction and adjacent instructions related to said first instruction from said set, if said first instruction is not aliased with said second instruction.

13. The system according to claim 9, further comprising:

means for determining a first instruction of said set of instructions;

means for determining whether variables of said set of instructions are ready for execution; and

means for determining whether a latency value from said launch point to said performance-degrading instruction is greater than a total latency value of said set of instructions including a miss latency of said performance-degrading instruction.

14. The system according to claim 9, further comprising:

means for marking said termination point subsequent to said performance-degrading instruction.

15. A computer readable medium containing executable instructions, which, when executed in a processing system, cause said processing system to perform a method comprising:

identifying at least one performance-degrading instruction from a plurality of instructions to be executed in a program;

defining a set of instructions within said program to prefetch said at least one performance-degrading instruction; and

marking at least one speculative bit of each instruction of said set of instructions to indicate a predetermined execution of said each instruction.

16. The computer readable medium according to claim 15, wherein said method further comprises:

inserting a launch point to launch said predetermined execution; and

inserting a termination point to terminate said predetermined execution.

17. The computer readable medium according to claim 15, wherein said identifying further comprises:

monitoring execution of said plurality of instructions; and

detecting said at least one performance-degrading instruction.

18. The computer readable medium according to claim 15, wherein said defining further comprises:

reducing a size of said set of instructions based on speculation and prediction techniques.

19. The computer readable medium according to claim 18, wherein said reducing further comprises:

determining whether a first instruction of said set of instructions is aliased with a second instruction within said set of instructions; and

removing said first instruction and adjacent instructions related to said first instruction from said set, if said first instruction is not aliased with said second instruction.

20. The computer readable medium according to claim 16, wherein inserting said launch point further comprises:

determining a first instruction of said set of instructions;

determining whether variables of said set of instructions are ready for execution; and

determining whether a latency value from said launch point to said performance-degrading instruction is greater than a total latency value of said set of instructions including a miss latency of said performance-degrading instruction.

21. The computer readable medium according to claim 16, wherein inserting said termination point further comprises:

marking said termination point subsequent to said performance-degrading instruction.

22. A system comprising:

a memory to store a plurality of instructions to be executed in a program; and

a processor coupled to said memory to identify at least one performance-degrading instruction from said plurality of instructions, to define a set of instructions within said program to prefetch said at least one performance-degrading instruction, and to mark at least one speculative bit of each instruction of said set of instructions to indicate a predetermined execution of said each instruction.

23. The system according to claim 22, wherein said processor further inserts a launch point to launch said predetermined execution and inserts a termination point to terminate said predetermined execution.

24. The system according to claim 22, wherein said processor further monitors execution of said plurality of instructions and detects said at least one performance-degrading instruction.

25. The system according to claim 22, wherein said processor further reduces a size of said set of instructions based on speculation and prediction techniques.

26. The system according to claim 25, wherein said processor further determines whether a first instruction of said set of instructions is aliased with a second instruction within said set of instructions, and removes said first instruction and adjacent instructions related to said first instruction from said set, if said first instruction is not aliased with said second instruction.

27. The system according to claim 23, wherein said processor further determines a first instruction of said set of instructions, determines whether variables of said set of instructions are ready for execution, and determines whether a latency value from said launch point to said performance-degrading instruction is greater than a total latency value of said set of instructions including a miss latency of said performance-degrading instruction.

28. The system according to claim 23, wherein said processor further marks said termination point subsequent to said performance-degrading instruction.