Twin bit cell flash memory device and its fabricating method

• US 20030075738A1
• Filed: 05/21/2002
• Published: 04/24/2003
• Est. Priority Date: 10/22/2001
• Status: Active Grant

• Current Assignee: Kent Kuohua Chang
• Original Assignee: Kent Kuohua Chang
• Inventors: Chang, Kent Kuohua
• Granted Patent: US 6,674,133 B2
• Time in Patent Office: Days
• US Class Current: 257/213
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si_1−xGe_x, x=0.05˜1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.

Claims

1. A twin bit cell flash memory device, the device comprising:

a semiconductor substrate;

a source and a drain positioned in a predetermined area of the semiconductor substrate, and the drain and the source separated by a predetermined distance;

a channel positioned on the surface of the semiconductor substrate between the source and the drain;

a first dielectric layer covering the surface of the channel;

a polysilicon germanium layer covering the surface of the first dielectric layer, the polysilicon germanium layer having an insulating region for separating the polysilicon germanium layer and forming two isolated conductive regions so as to form a twin bit cell structure;

a second dielectric layer covering the surface of the polysilicon germanium layer; and

a gate covering the surface of the second dielectric layer;

wherein each conductive region serves as a charge trapping layer so as to receive and store electrons injected into the conductive region to generate a respective bit.

2. The flash memory device of claim 1 wherein the semiconductor substrate is a P-type substrate, and the source and the drain are both N-type doped areas.

3. The flash memory device of claim 1 wherein the semiconductor substrate is an N-type substrate, and the source and the drain are both P-type doped areas.

4. The flash memory device of claim 1 wherein the chemical composition of the polysilicon germanium layer is Si₁₋

xGe_xx=0.05˜

1.0.

5. The flash memory device of claim 1 wherein the insulating region is formed by implanting a high concentration of oxygen dopant into the polysilicon germanium layer, and then performing a thermal process.

6. The flash memory device of claim 5 wherein the high concentration of oxygen dopant is formed by an oxygen ion implantation process, the implanting dosage being approximately 1˜

2×

10¹⁸/cm², the implanting energy ranging from 20 KeV to 80 KeV.

7. The flash memory device of claim 5 wherein the thermal process is a high temperature annealing process with a temperature range of 950°

C. to 1150°

C.

8. The flash memory device of claim 1 wherein the insulating region is formed by implanting a high concentration of nitrogen dopant into the polysilicon germanium layer, and then performing a thermal process.

9. The flash memory device of claim 1 wherein an oxide layer is also formed on the exposed side walls of each conductive region.