Stacked capacitor and method for fabricating the same

• US 20030075753A1
• Filed: 09/13/2002
• Published: 04/24/2003
• Est. Priority Date: 09/14/2001
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Winbond Electronics Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Winbond Electronics Corporation
• Inventors: Fukuda, Masatoshi, Chu, Chung-Ming, Suzuki, Tosiya, Kiyotoshi, Masuhiro, Yang, Min-Chieh
• Application Number:
  US10/243,554
• Publication Number:
  US 20030075753A1
• Time in Patent Office: Days
• US Class Current: 257/308
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers

Abstract

A stacked capacitor on a contact plug of a semiconductor substrate and the method for fabricating the same. A cylindrical conductive layer is formed upon a contact plug of a semiconductor substrate as a lower electrode of a stacked capacitor and there is an opening in the cylindrical conductive layer. A barrier layer is deposited inside the opening of the cylindrical conductive layer and fills a portion of the opening. A capacitor dielectric layer is deposited on the cylindrical conductive layer and on the barrier layer and an upper electrode layer is formed on the capacitor dielectric layer to complete the stacked capacitor.

Claims

1. A stacked capacitor on a contact plug of a semiconductor substrate, comprising:

a cylindrical conductive layer as a lower electrode of the stacked capacitor, wherein an opening is in the cylindrical conductive layer;

a barrier layer inside the opening of the cylindrical conductive layer and filling a portion of the opening;

a capacitor dielectric layer on the cylindrical conductive layer and the barrier layer; and

an upper electrode layer on the capacitor dielectric layer.

2. The stacked capacitor as claimed in claim 1, wherein the material of the cylindrical conductive layer is Pt, Ru, Ir, IrO₂, or RuO₂.

3. The stacked capacitor as claimed in claim 1, wherein the material of the cylindrical conductive layer is Ru.

4. The stacked capacitor as claimed in claim 1, wherein the material of the barrier layer is SiN, Ta₂O₅ or Al₂O₃.

5. The stacked capacitor as claimed in claim 1, wherein the material of the barrier layer is Ta₂O₅.

6. The stacked capacitor as claimed in claim 1, wherein the material of the capacitor dielectric layer is zirconate titanate (PZT), strontium bismuth tantalate (SBT), BaSrTiO₃ (BST) or SrTiO₃ (ST).

7. The stacked capacitor as claimed in claim 1, wherein the material of the upper electrode layer is Pt, Ir or Ru.

8. The stacked capacitor as claimed in claim 1, wherein the contact plug comprises W.

9. The stacked capacitor as claimed in claim 8, wherein another barrier layer is between the contact plug and cylindrical conductive layer.

10. The stacked capacitor as claimed in claim 1, wherein the contact plug comprises Ru.

11. A stacked capacitor on a contact plug of a semiconductor substrate, comprising:

a cylindrical conductive layer as a lower electrode of the stacked capacitor, wherein an opening is in the cylindrical conductive layer;

a barrier layer lining the lower portion and bottom of the opening of the cylindrical conductive layer;

a capacitor dielectric layer on the cylindrical conductive layer and the barrier layer; and

an upper electrode layer on the capacitor dielectric layer.

12. The stacked capacitor as claimed in claim 11, wherein the material of the cylindrical conductive layer is Pt, Ru, Ir, IrO₂, or RuO₂.

13. The stacked capacitor as claimed in claim 11, wherein the material of the cylindrical conductive layer is Ru.

14. The stacked capacitor as claimed in claim 11, wherein the material of the barrier layer is SiN, Ta₂O₅ or Al₂O₃.

15. The stacked capacitor as claimed in claim 11, wherein the material of the barrier layer is Ta₂O₅.

16. The stacked capacitor as claimed in claim 11, wherein the material of the capacitor dielectric layer is zirconate titanate (PZT), strontium bismuth tantalate (SBT), BaSrTiO₃ (BST) or SrTiO₃ (ST).

17. The stacked capacitor as claimed in claim 11, wherein the material of the upper electrode layer is Pt, Ir or Ru.

18. The stacked capacitor as claimed in claim 11, wherein the contact plug comprises W.

19. The stacked capacitor as claimed in claim 18, wherein another barrier layer is formed between the contact plug and the cylindrical conductive layer.

20. The stacked capacitor as claimed in claim 11, wherein the contact plug comprises Ru.

21. A method of fabricating a stacked capacitor, comprising the steps of:

(a) providing a semiconductor substrate comprising a first insulating layer thereon and a contact plug embedded in the first insulating layer;

(b) forming a second insulating layer an a third insulating layer on the semiconductor substrate in sequence;

(c) removing a portion of the second insulating layer and the third insulating layer to form an opening and exposing the contact plug by lithography and etching;

(d) depositing a first barrier layer and a first conductive layer in sequence on the opening and the third insulating layer;

(e) depositing a second barrier layer on the first conductive layer and recessing the second barrier layer untill the surface of the second barrier layer is below the top of the opening;

(f) removing the first conductive layer beyond the opening and forming a cylindrical conductive layer in the opening as a lower electrode of the stacked capacitor;

(g) recessing the third insulating layer and the first barrier layer untill the second insulating layer is exposed;

(h) forming a capacitor dielectric layer on the second barrier and the cylindrical conductive layer; and

(i) forming an upper electrode layer on the capacitor dielectric layer.

22. The method as claimed in claim 21, wherein the materials of the first insulating layer and the third insulating layer are silicon oxide.

23. The method as claimed in claim 21, wherein the material of the second insulating layer is silicon nitride.

24. The method as claimed as claim 21, wherein the contact plug comprises W.

25. The method as claimed in claim 21, wherein the contact plug comprises Ru.

26. The method as claimed in claim 21, wherein the material of the first barrier is TiN, TiSiN, or TiAlN.

27. The method as claimed in claim 21, wherein the material of the second barrier is SiN, Ta₂O₅ or Al₂O₃.

28. The method as claimed in claim 21, wherein the material of the second barrier is Ta₂O₅.

29. The method as claimed in claim 21, wherein the material of the first conductive layer is Pt, Ru, Ir, IrO₂, or RuO₂.

30. The method as claimed as in claim 21, wherein the material of the capacitor dielectric layer is zirconate titanate (PZT), strontium bismuth tantalate (SBT), BaSrTiO₃ (BST) or SrTiO₃ (ST).

31. The method as claimed in claim 21, wherein the material of the upper electrode is Pt, Ir and Ru.

32. The method as claimed in claim 21, wherein in the step (e) depositing the second barrier layer on the first conductive layer fills up the opening with the second barrier layer.

33. The method as claimed in claim 21, wherein in the step (e) depositing the second barrier layer on the first conductive layer does not fill up the opening with the second barrier layer.