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Method to form a self-aligned CMOS inverter using vertical device integration

  • US 20030075758A1
  • Filed: 09/12/2002
  • Published: 04/24/2003
  • Est. Priority Date: 10/18/2001
  • Status: Active Grant
First Claim
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1. A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device comprising:

  • providing a substrate comprising silicon implanted oxide wherein an oxide layer is sandwiched between underlying and overlying silicon layers;

    selectively implanting ions into a first part of said overlying silicon layer to form a drain, channel region, and source for an NMOS transistor wherein said drain is formed directly overlying said oxide layer, wherein said channel region is formed overlying said drain, and wherein said source is formed overlying said channel region;

    selectively implanting ions into a second part of said overlying silicon layer to form a drain, channel region, and source for a PMOS transistor wherein said drain is formed directly overlying said oxide layer, wherein said PMOS channel region is formed overlying said drain, wherein said source is formed overlying said channel region, and wherein said drain is in contact with said NMOS transistor drain;

    etching a gate trench through said NMOS and PMOS sources and channel regions wherein said gate trench terminates at said NMOS and PMOS drains and wherein said gate trench exposes sidewalls of said NMOS and PMOS channel regions;

    forming a gate oxide layer overlying said NMOS and PMOS channel regions and lining said gate trench;

    depositing a polysilicon layer overlying said gate oxide layer; and

    etching back said polysilicon layer to form polysilicon sidewalls and to thereby form gates for said closely-spaced, vertical NMOS and PMOS transistor pair in the manufacture of the integrated circuit device.

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