Method to form a self-aligned CMOS inverter using vertical device integration
First Claim
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1. A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device comprising:
- providing a substrate comprising silicon implanted oxide wherein an oxide layer is sandwiched between underlying and overlying silicon layers;
selectively implanting ions into a first part of said overlying silicon layer to form a drain, channel region, and source for an NMOS transistor wherein said drain is formed directly overlying said oxide layer, wherein said channel region is formed overlying said drain, and wherein said source is formed overlying said channel region;
selectively implanting ions into a second part of said overlying silicon layer to form a drain, channel region, and source for a PMOS transistor wherein said drain is formed directly overlying said oxide layer, wherein said PMOS channel region is formed overlying said drain, wherein said source is formed overlying said channel region, and wherein said drain is in contact with said NMOS transistor drain;
etching a gate trench through said NMOS and PMOS sources and channel regions wherein said gate trench terminates at said NMOS and PMOS drains and wherein said gate trench exposes sidewalls of said NMOS and PMOS channel regions;
forming a gate oxide layer overlying said NMOS and PMOS channel regions and lining said gate trench;
depositing a polysilicon layer overlying said gate oxide layer; and
etching back said polysilicon layer to form polysilicon sidewalls and to thereby form gates for said closely-spaced, vertical NMOS and PMOS transistor pair in the manufacture of the integrated circuit device.
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Abstract
A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer, to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.
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Citations
34 Claims
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1. A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device comprising:
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providing a substrate comprising silicon implanted oxide wherein an oxide layer is sandwiched between underlying and overlying silicon layers;
selectively implanting ions into a first part of said overlying silicon layer to form a drain, channel region, and source for an NMOS transistor wherein said drain is formed directly overlying said oxide layer, wherein said channel region is formed overlying said drain, and wherein said source is formed overlying said channel region;
selectively implanting ions into a second part of said overlying silicon layer to form a drain, channel region, and source for a PMOS transistor wherein said drain is formed directly overlying said oxide layer, wherein said PMOS channel region is formed overlying said drain, wherein said source is formed overlying said channel region, and wherein said drain is in contact with said NMOS transistor drain;
etching a gate trench through said NMOS and PMOS sources and channel regions wherein said gate trench terminates at said NMOS and PMOS drains and wherein said gate trench exposes sidewalls of said NMOS and PMOS channel regions;
forming a gate oxide layer overlying said NMOS and PMOS channel regions and lining said gate trench;
depositing a polysilicon layer overlying said gate oxide layer; and
etching back said polysilicon layer to form polysilicon sidewalls and to thereby form gates for said closely-spaced, vertical NMOS and PMOS transistor pair in the manufacture of the integrated circuit device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method to form an inverter with a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device comprising:
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selectively implanting ions into a first part of said overlying silicon layer to form a drain, channel region, and source for an NMOS transistor wherein said drain is formed directly overlying said oxide layer, wherein said channel region is formed overlying said drain, and wherein said source is formed overlying said channel region;
selectively implanting ions into a second part of said overlying silicon layer to form a drain, channel region, and source for a PMOS transistor wherein said drain is formed directly overlying said oxide layer, wherein said PMOS channel region is formed overlying said drain, wherein said source is formed overlying said channel region, and wherein said drain is in contact with said NMOS transistor drain;
etching a gate trench through said NMOS and PMOS sources and channel regions wherein said gate trench terminates at said NMOS and PMOS drains and wherein said gate trench exposes sidewalls of said NMOS and PMOS channel regions;
forming a gate oxide layer overlying said NMOS and PMOS channel regions and lining said gate trench;
depositing a polysilicon layer overlying said gate oxide layer;
etching back said polysilicon layer to form polysilicon sidewalls and to thereby form gates for said closely-spaced, vertical NMOS and PMOS transistor pair;
depositing an interlevel dielectric layer overlying said closely-spaced, vertical NMOS and PMOS transistor pair after said step of etching back said polysilicon layer;
etching openings through said interlevel dielectric layer to expose said PMOS source and drain and said NMOS source and drain;
thereafter forming a metal silicide layer in said PMOS source and drain and said NMOS source and drain;
depositing a metal layer overlying said interlevel dielectric layer and said overlying silicon layer; and
patterning said metal layer to form connective lines to complete said inverter in the manufacture of the integrated circuit device. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A closely-spaced, vertical NMOS and PMOS transistor pair comprising:
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a substrate comprising silicon implanted oxide wherein an oxide layer is sandwiched between underlying and overlying silicon layers;
a vertical NMOS transistor in said overlying silicon layer, said vertical NMOS transistor comprising;
a drain overlying said oxide layer;
a channel region overlying a part of said drain;
a source overlying said channel region;
a gate trench that exposes a top surface of said drain and a vertical surface of said channel region; and
a comprising a polysilicon sidewall spacer adjacent to said vertical surface of said channel region with a gate oxide layer therebetween; and
a vertical PMOS transistor in said overlying silicon layer, said PMOS transistor comprising;
a drain overlying said oxide layer wherein said drain contacts said vertical NMOS transistor drain;
a channel region overlying a part of said drain;
a source overlying said channel region; and
a gate trench that exposes a top surface of said drain and a vertical surface of said channel region; and
a gate comprising a polysilicon sidewall spacer adjacent to said vertical surface of said channel region with a gate oxide layer therebetween. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification
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Current AssigneeChartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
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Original AssigneeChartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
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InventorsMeng Lee, James Yong, Chan, Lap, Pan, Yang, Quek, Elgin, Pradeep, Yelehanka Ramachandramurthy, Zheng, Jia Zhen, Leung, Ying Keung, Sundaresan, Ravi
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current257/329
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CPC Class CodesH01L 21/823885 with a particular manufactu...H01L 21/84 the substrate being other t...H01L 27/1203 the substrate comprising an...H01L 29/66666 Vertical transistors H01L29...
