Semiconductor device, method for manufacturing the same, and plating solution

• US 20030075808A1
• Filed: 08/13/2002
• Published: 04/24/2003
• Est. Priority Date: 08/13/2001
• Status: Active Grant

• Current Assignee: Ebara Corporation
• Original Assignee: Ebara Corporation
• Inventors: Kimura, Norio, Inoue, Hiroaki, Wang, Xinming, Kanayama, Makoto, Matsumoto, Moriji
• Granted Patent: US 7,060,618 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: C23C 18/1608 from pretreatment step, i.e. selective pre-treatment
• CPC Class Codes: C23C 18/1632 Features specific for the apparatus, e.g. layout of cells and of its equipment, multiple cells
• CPC Class Codes: C23C 18/1653 Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
• CPC Class Codes: C23C 18/32 Coating with nickel, cobalt or mixtures thereof with phosphorus or boron C23C18/50 takes precedence
• CPC Class Codes: C23C 18/48 Coating with alloys
• CPC Class Codes: C23C 18/50 with alloys based on iron, cobalt or nickel
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention relates to relates to a semiconductor device and a method for manufacturing the same having an embedded interconnect structure in which an electric conductor, such as copper or silver, is embedded in fine recesses for interconnects formed in the surface of a semiconductor substrate, and having a protective film formed on the surface of the interconnects to protect the interconnects. The semiconductor device having an embedded interconnect structure, including a protective film formed selectively on the surface of exposed interconnects, wherein the protective film has a flattened surface.

Claims

1. A semiconductor device having an embedded interconnect structure, comprising a protective film formed on the surface of exposed interconnects, wherein the protective film has a flattened surface.

2. The semiconductor device according to claim 1, wherein the protective film is composed of at least one of Co, a Co alloy, Ni and a Ni alloy.

3. A semiconductor device having an embedded interconnect structure, comprising an interconnects-protective film formed selectively on the surface of exposed interconnects, wherein the protective film has an amorphous phase.

4. The semiconductor device according to claim 3, wherein the interconnects-protective film is composed of a Ni alloy, a Co alloy or a Cu alloy formed by electroless plating.

5. The semiconductor device according to claim 3, wherein an interconnect material of the embedded interconnect structure is composed of copper, a copper alloy, silver or a silver alloy.

11. The semiconductor device according to claim 4, wherein the seed layer is composed of an amorphous Co—

B alloy, and the protective film is composed of an amorphous Co—

W—

B alloy or an amorphous Co—

W—

P alloy.

6. A semiconductor device having an embedded interconnect structure, comprising an interconnects-protective film formed selectively on the surface of exposed interconnects, wherein the interconnects-protective film is a nonmagnetic film.

7. The semiconductor device according to claim 6, wherein the interconnects-protective film is composed of a Ni alloy, a Co alloy or a Cu alloy formed by electroless plating.

8. The semiconductor device according to claim 6, wherein an interconnect material of the embedded interconnect structure is composed of copper, a copper alloy, silver or a silver alloy.

9. A semiconductor device having an embedded interconnect structure, comprising a protective film formed selectively on the surface of exposed interconnects, wherein the protective film is obtained by a process comprising carrying out a pretreatment of the surface of exposed interconnects, and then forming the protective film selectively on the pretreated surface of exposed interconnects.

10. The semiconductor device according to claim 9, wherein a seed layer, which acts as a catalyst in electroless plating in the next step, is formed by the pretreatment selectively on the surface of exposed interconnects, and the protective film is formed selectively on the surface of the seed layer.

12. A semiconductor device comprising interconnects composed of a copper alloy, said interconnects having been formed by embedding the copper alloy in fine recesses for interconnects provided in the surface of a substrate, wherein the copper alloy is an alloy of copper and a metal in which the metal does not form a solid solution with copper.

13. The semiconductor device according to claim 12, wherein the copper alloy is a copper-silver alloy, a copper-cobalt alloy, a copper-tin alloy, or a copper-boron alloy.

14. The semiconductor device according to claim 13, wherein the copper content of the copper alloy is 90 to 99.99 at %.

15. A semiconductor device having an embedded interconnect structure, comprising a protective film composed of a copper alloy formed selectively on the surface of exposed interconnects, wherein the copper alloy is an alloy of copper and a metal in which the metal does not form a solid solution with copper.

16. The semiconductor device according to claim 15, wherein the copper alloy is a copper-silver alloy, a copper-cobalt alloy, a copper-tin alloy, or a copper-boron alloy.

17. The semiconductor device according to claim 16, wherein the copper content of the copper alloy is 90 to 99.99 at %.

18. A method for manufacturing a semiconductor device, comprising:

forming a protective film by electroless plating selectively on the surface of exposed interconnects in a semiconductor device having an embedded interconnect structure; and

flattening the surface of the semiconductor device having the protective film thus formed.

19. The method for manufacturing a semiconductor device according to claim 18, comprising:

embedding an electric conductor by plating in recesses for interconnects provided in the surface of a semiconductor device having an embedded interconnect structure;

heat-treating the electric conductor;

flattening the surface of the semiconductor device by polishing;

forming a protective film by electroless plating selectively on the surface of exposed interconnects;

and flattening the surface of the semiconductor device by polishing.

20. The method for manufacturing a semiconductor device according to claim 19, wherein a pre-plating treatment is carried out before the electroless plating to selectively form the protective film.

21. The method for manufacturing a semiconductor device according to claim 19, comprising:

embedding an electric conductor by plating in recesses for interconnects provided in the surface of a substrate;

heat-treating the electric conductor;

flattening the surface of the heat-treated substrate by polishing;

cleaning the flattened surface of the substrate; and

forming a protective film by electroless plating selectively on the surface of exposed interconnects in the cleaned substrate.

22. The method for manufacturing a semiconductor device according to claim 21, wherein the cleaning is carried out so that an electric conductor contamination on an insulating film in the surface of the substrate is reduced to 5×

10⁵ atoms/cm² or less.

23. A method for manufacturing a semiconductor device, comprising carrying out electroless plating of the surface of a semiconductor device having an embedded interconnect structure to form an interconnects-protective film selectively on the surface of exposed interconnects, wherein the protective film has an amorphous phase.

24. The method for manufacturing a semiconductor device according to claim 23, wherein the interconnects-protective film is composed of a Ni alloy, a Co alloy or a Cu alloy.

25. The method for manufacturing a semiconductor device according to claim 23, comprising:

embedding an electric conductor by plating in recesses for interconnects provided in the surface of a semiconductor device having an embedded interconnect structure;

heat-treating the electric conductor;

flattening the surface of the semiconductor device by chemical mechanical polishing; and

forming an interconnects-protective film, having an amorphous phase by electroless plating selectively on the surface of exposed interconnects in the semiconductor device.

26. A method for manufacturing a semiconductor device, comprising carrying out electroless plating of the surface of a semiconductor device having an embedded interconnect structure to form an interconnects-protective film selectively on the surface of exposed interconnects, wherein the protective film is a nonmagnetic film.

27. The method for manufacturing a semiconductor device according to claim 26, wherein the interconnects-protective film is composed of a Ni alloy, a Co alloy or a Cu alloy.

28. The method for manufacturing a semiconductor device according to claim 26, comprising:

embedding an electric conductor by plating in recesses for interconnects provided in the surface of a semiconductor device having an embedded interconnect structure;

heat-treating the electric conductor;

flattening the surface of the semiconductor device by chemical mechanical polishing; and

forming an interconnects-protective film, which is a nonmagnetic film, by electroless plating selectively on the surface of exposed interconnects in the semiconductor device.

29. A method for manufacturing a semiconductor device, comprising:

carrying out a selective pretreatment of the surface of exposed interconnects in a semiconductor device having an embedded interconnect structure; and

forming a protective film by electroless plating selectively on the pretreated surface of interconnects.

30. The method for manufacturing a semiconductor device according to claim 29, wherein a seed layer, which acts as a catalyst in the electroless plating, is formed by the pretreatment selectively on the surface of exposed interconnects, and the protective film is formed selectively on the seed layer.

31. The method for manufacturing a semiconductor device according to claim 30, wherein the seed layer is composed of an amorphous Co—

B alloy, and the protective film is composed of an amorphous Co—

W—

B alloy or an amorphous Co—

W—

P alloy.

32. The method for manufacturing a semiconductor device according to claim 29, comprising:

embedding an electric conductor by plating in recesses for interconnects provided in the surface of a semiconductor device having an embedded interconnect structure;

heat-treating the electric conductor;

flattening the surface of the semiconductor device by chemical mechanical polishing;

carrying out a pretreatment of the surface of exposed surface in the semiconductor device; and

forming a protective film by electroless plating selectively on the pretreated surface of interconnects.

33. A method for manufacturing a semiconductor device, comprising plating the surface of a substrate to embed a copper alloy in fine recesses for interconnects provided in the surface of the substrate, thereby forming interconnects, wherein the copper alloy is an alloy of copper and a metal in which the metal does not form a solid solution with copper.

34. The method for manufacturing a semiconductor device according to claim 33, wherein the copper alloy is a copper-silver alloy, a copper-cobalt alloy, a copper-tin alloy, or a copper-boron alloy.

35. The method for manufacturing a semiconductor device according to claim 34, wherein the copper content of the copper alloy is 90 to 99.99 at %.

36. A method for manufacturing a semiconductor device, comprising plating the surface of a semiconductor device having an embedded interconnect structure, thereby forming a protective film composed of a copper alloy selectively on at least part of exposed interconnects, wherein the copper alloy is an alloy of copper and a metal in which the metal does not form a solid solution with copper.

37. The method for manufacturing a semiconductor device according to claim 36, wherein the copper alloy is a copper-silver alloy, a copper-cobalt alloy, a copper-tin alloy, or a copper-boron alloy.

38. The method for manufacturing a semiconductor device according to claim 37, wherein the copper content of the copper alloy is 90 to 99.99 at %.

41. An apparatus for manufacturing a semiconductor device, comprising:

a first plating unit for embedding an electric conductor in recesses for interconnects provided in the surface of a substrate;

a first polishing unit for polishing the surface of the substrate in which the electric conductor is embedded;

a second plating unit for forming a protective film selectively on the surface of exposed interconnects after the polishing; and

a second polishing unit for polishing the surface of the substrate in which the protective film is formed.

42. The method for manufacturing a semiconductor device according to claim 41 further comprising a heat treatment unit for heat-treating the electric conductor embedded in the substrate.

43. The method for manufacturing a semiconductor device according to claim 41 further comprising a third plating unit for forming a seed layer, which acts as a catalyst in the plating in the second plating unit, selectively on the surface of interconnects prior to forming the protective film selectively on the surface of interconnects in the second plating unit.

44. The apparatus for manufacturing a semiconductor device according to claim 41 further comprising a cleaning unit for cleaning the surface of the substrate which has been flattened by the polishing in the first polishing unit.

45. The apparatus for manufacturing a semiconductor device according to claim 44, wherein the surface of the substrate is cleaned in the cleaning unit so that an electric conductor contamination on an insulating film in the surface of the substrate is reduced to 5×

10⁵ atoms/cm² or less.

46. A plating solution comprising copper ions, metal ions of a metal, said metal being capable of forming with copper a copper alloy in which said metal does not form a solid solution with copper, a complexing agent, and a reducing agent free from alkali metal.

47. The plating solution according to claim 46, wherein said metal ions are silver ions, cobalt ions or tin ions.

48. The plating solution according to claim 46, wherein the reducing agent is an alkylamine borane.

49. The plating solution according to claim 46 further comprising at least one of a stabilizer selected from a sulfur compound, a nitrogen compound, a heavy metal compound or a mixture thereof, and a surfactant.

50. The plating solution according to claim 46, wherein the pH of the plating solution is adjusted to 5-14 with a pH adjusting agent free from alkali metal.