Method and system for wafer and device level testing of an integrated circuit

• US 20030076125A1
• Filed: 05/21/2002
• Published: 04/24/2003
• Est. Priority Date: 09/22/2000
• Status: Active Grant

• Current Assignee: Don Mccord
• Original Assignee: Don Mccord
• Inventors: McCord, Don
• Granted Patent: US 6,927,591 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G01R 31/30 Marginal testing, e.g. by varying supply voltage testing computers during standby operation or idle time G06F11/22
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 7/1066 Output synchronization

Abstract

A tester comprises test logic and a connector for at least one device under test. The connector, which may comprise a wafer probe for dice on a wafer or a test fixture or either packaged integrated circuit devices or circuit board modules, has connections for the device under test that present an impedance selected to emulate the characteristic impedance of an end-use environment of the device under test. For example, in an embodiment in which the device under test comprises DDR memory and the end-use environment is a DDR memory module, the characteristic impedance is approximately 60 ohms. Thus, the tester of the present invention can accurately simulate operational behavior in an end-use environment of the device under test. Because this accurate simulation is available even for dice on a wafer, the needless expense associated with packaging defective dies and assembling defective dies into modules can be avoided. The test logic, which is couplet to the connector for communication with the device under test, transfers test commands and test data to (tic device under test. The test data and commands are utilized to perform multiple types of tests, including tests of the memory core and internal logic of the device under test. In this manner, the need for multiple types of testers is reduced or eliminated.

Claims

1. A tester for testing memory dice on a wafer, said tester comprising:

a wafer probe card having connections for at least one device under test that comprises a double data rate (DDR) memory die on a wafer, wherein the connections of the wafer probe card present an impedance selected to emulate the characteristic impedance of an end-use environment for a packaged device containing the at least one memory die; and

tester logic, coupled to the wafer probe card, that communicates test data with the device under test via the wafer probe card.

2. The tester of claim 1, wherein the end-use environment is one of a DDR memory bus and a DDR memory module and the characteristic impedance is approximately 60 ohms.

3. The tester of claim 1, wherein the connections comprise microsprings.

4. The tester of claim 1, said wafer probe card including a variable impedance network having a dynamically alterable impedance selected by the tester logic.

5. The tester of claim 1, wherein said wafer probe card includes at least one dummy packaged device to simulate operating characteristics of the end-use environment.

6. The tester of claim 1, wherein the at least device under test includes memory cells, and wherein the tester logic includes means for communicating voltage signals to device under test to alter which of the memory cells are active for operations to specific address locations.

7. The tester of claim 1, wherein the tester logic includes a DDR memory controller that interfaces with the wafer probe card.

8. The tester of claim 1, wherein the tester logic further comprises:

a clock generator that generates at least one clock signal received by the tester logic and at least one timing signal that coordinates data transfer between the tester logic and the at least one device under test; and

one or more delay elements that selectively alter the relative phases of the at least one clock signal and the at least one timing signal to test timing sensitivity of the at least one device under test.

9. The tester of claim 8, wherein during a WRITE operation the one or more delay elements delay the at least one timing signal received by the at least one device under test relative to write data.

10. The tester of claim 9, wherein the at least one timing signal received by the at least one device under test during the WRITE operation comprises a data strobe (DQS) signal.

11. The tester of claim 10, wherein the tester logic outputs to the device under test data signals and row and column signals while the one or more delay elements delay the data strobe (DQS) signal to the device under test to test sensitivity of the device under test to input hold and input setup timing parameters.

12. The tester of claim 8, wherein during a READ operation the one or more delay elements delay the at least one timing signal to the tester logic relative to read data received from the device under test.

13. The tester of claim 12, wherein the at least one timing signal received by the tester logic comprises a data strobe (DQS) signal.

14. The tester of claim 1, wherein the tester logic further comprises:

a clock generator that generates at least one clock signal received by the tester logic and at least one timing signal that coordinates data transfer between the tester logic and the at least one device under test; and

one or more delay elements that selectively alter the phase of data signals communicated between the at least one device under test and the tester logic to test timing sensitivity of the at least one device under test.

15. The tester of claim 14, wherein the at least one timing signal is received by the at least one device under test from the tester logic and comprises a data strobe signal;

and

said tester logic includes one or more delay elements that during a WRITE operation selectively delay data signals received by the at least one device under test from the tester logic to test timing sensitivity of the at least one device under test for input hold and input setup timing parameters.

16. The tester of claim 14, wherein the at least one timing signal is received by the tester logic from the at least one die and comprises a data strobe signal;

and

said tester logic includes one or more delay elements that during a READ operation selectively delay data signals received by the tester logic from the at least one device under test to test timing sensitivity of the at least one device under test.

17. The tester of claim 8, wherein the one or more delay elements shift phases of both data signals and the at least one timing signal in small increments.

18. The tester of claim 17, wherein:

said tester further comprises a power subsystem including a variable reference voltage supply and variable supply voltage supply coupled to said wafer probe card to supply a reference voltage and a supply voltage to said at least one device under test through said connections; and

said tester logic comprises means for testing sensitivity of the device under test to timing and voltage combinations by setting the one or more delay elements to delay data strobe and data signals while setting at least one of the reference voltage and supply voltages outside of normal operating voltage ranges.

19. The tester of claim 18, wherein:

the wafer probe card comprises at least one variable impedance; and

the tester logic comprises means for varying the variable impedance to test sensitivity of said at least one device under test while testing with multiple combinations of timing signal and data delays and reference and supply voltages.

20. The tester of claim 8, wherein:

said tester further comprises a power subsystem including a variable reference voltage supply coupled to said wafer probe card to supply a reference voltage to said at least one device under test through said connections; and

the tester logic comprises means for varying the reference voltage to simulate variation of input voltage levels to test sensitivity of said at least one device under test to input voltage variations.

21. The tester of claim 1, wherein said tester logic comprises a tester logic interface to which a host system communicates memory access requests to access the device under test.

22. The tester of claim 21, and further comprising the host system coupled to the tester logic interface, wherein the host system accesses the device under test on the wafer via the tester logic and wafer probe card by communicating memory access requests to the tester logic interface.

23. A tester for packaged integrated circuit memory devices, said tester comprising:

a test fixture having connections for at least one device under test that comprises a packaged integrated circuit double data rate (DDR) memory device, wherein the connections of the test fixture present an impedance selected to emulate the characteristic impedance of an end-use environment for the at least one device under test; and

tester logic, coupled to the test fixture, that communicates test data with the at least one packaged memory device via the test fixture.

24. The tester of claim 23, wherein the end-use environment is a DDR memory module and the characteristic impedance is approximately 60 ohms.

25. The tester of claim 23, wherein the connections comprise microsprings.

26. The tester of claim 23, said test fixture including a variable impedance network having a dynamically alterable impedance selected by the tester logic.

27. The tester of claim 23, wherein said test fixture includes at least one dummy packaged integrated circuit device to simulate operating characteristics of the end-use environment.

28. The tester of claim 23, wherein the tester logic includes a DDR memory controller that interfaces with the test fixture.

29. The tester of claim 23, wherein the tester logic further comprises:

a clock generator that generates at least one clock signal received by the tester logic and at least one timing signal that coordinates data transfer between the tester logic and the at least one device under test; and

one or more delay elements that selectively alter the relative phases of the at least one clock signal and the at least one timing signal to test timing sensitivity of the at least one device under test.

30. The tester of claim 29, wherein during a WRITE operation the one or more delay elements delay the at least one timing signal received by the at least one device under test relative to write data.

31. The tester of claim 30, wherein the at least one timing signal received by the at least one device under test during the WRITE operation comprises a data strobe (DQS) signal.

32. The tester of claim 31, wherein the tester logic outputs to the device under test data signals and row and column signals while the one or more delay elements delay the data strobe (DQS) signal to the device under test to test sensitivity of the device under test to input hold and input setup timing parameters.

33. The tester of claim 30, wherein during a READ operation the one or more delay elements delay the at least one timing signal to the tester logic relative to read data received from the device under test.

34. The tester of claim 33, wherein the at least one timing signal received by the tester logic comprises a data strobe (DQS) signal.

35. The tester of claim 23, wherein the tester logic further comprises:

a clock generator that generates at least one clock signal received by the tester logic and at least one timing signal that coordinates data transfer between the tester logic and the at least one device under test; and

one or more delay elements that selectively alter the phase of data signals communicated between the at least one device under test and the tester logic to test timing sensitivity of the at least one device under test.

36. The tester of claim 35, wherein the at least one timing signal is received by the at least one device under test from the tester logic and comprises a data strobe signal;

and

said tester logic includes one or more delay elements that during a WRITE operation selectively delay data signals received by the at least one device under test from the tester logic to test timing sensitivity of the at least one device under test for input hold and input setup timing parameters.

37. The tester of claim 35, wherein the at least one timing signal is received by the tester logic from the at least one die and comprises a data strobe signal;

and

said tester logic includes one or more delay elements that during a READ operation selectively delay data signals received by the tester logic from the at least one device under test to test timing sensitivity of the at least one device under test.

38. The tester of claim 29, wherein the one or more delay elements shift phases of both data signals and the at least one timing signal in small increments.

39. The tester of claim 38, wherein:

said tester further comprises a power subsystem including a variable reference voltage supply and variable supply voltage supply coupled to said wafer probe card to supply a reference voltage and a supply voltage to said at least one device under test through said connections; and

said tester logic comprises means for testing sensitivity of the device under test to timing and voltage combinations by setting the one or more delay elements to delay data strobe and data signals while setting at least one of the reference voltage and supply voltages outside of normal operating voltage ranges.

40. The tester of claim 39, wherein:

the test fixture comprises at least one variable impedance; and

the tester logic comprises means for varying the variable impedance to test sensitivity of said at least one device under test while testing with multiple combinations of timing signal and data delays and reference and supply voltages.

41. The tester of claim 29, wherein:

said tester further comprises a power subsystem including a variable reference voltage supply coupled to said test fixture to supply a reference voltage to said at least one device under test through said connections; and

the tester logic comprises means for varying the reference voltage to simulate variation of input voltage levels to test sensitivity of said at least one device under test to input voltage variations.

42. The tester of claim 23, wherein said tester logic comprises a tester logic interface to which a host system communicates memory access requests to access the device under test.

43. The tester of claim 42, and further comprising the host system coupled to the tester logic interface, wherein the host system accesses the device under test on the wafer via the tester logic and wafer probe card by communicating memory access requests to the tester logic interface.

44. A tester for memory modules, said tester comprising:

a test fixture having collections for at least one device under test that comprises a double data rate (DDR) memory module, wherein the connections of the test fixture present an impedance selected to emulate the characteristic impedance of an end-use environment for the at least one memory module; and

tester logic, coupled to the test fixture, that communicates test data with the at least one device under test via the test fixture.

45. The tester of claim 44, wherein the end-use environment is a host system that employs at least one DDR memory module and the characteristic impedance is approximately 60 ohms.

46. The tester of claim 44, wherein the connections comprise microsprings.

47. The tester of claim 44, said test fixture including a variable impedance network having a dynamically alterable impedance selected by the tester logic.

48. The tester of claim 44, wherein the tester logic includes a DDR memory controller that interfaces with the test fixture.

49. The tester of claim 44, wherein the tester logic further comprises:

a clock generator that generates at least one clock signal received by the tester logic and at least one timing signal that coordinates data transfer between the tester logic and the at least one device under test; and

one or more delay elements that selectively alter the relative phases of the at least one clock signal and the at least one timing signal to test timing sensitivity of the at least one device under test.

50. The tester of claim 49, wherein during a WRITE operation the one or more delay elements delay the at least one timing signal received by the at least one device under test relative to write data.

51. The tester of claim 50, wherein the at least one timing signal received by the at least one device under test during the WRITE operation comprises a data strobe (DQS) signal.

52. The tester of claim 51, wherein the tester logic outputs to the device under test data signals and row and column signals while the one or more delay elements delay the data strobe (DQS) signal to the device under test to test sensitivity of the device under test to input hold and input setup timing parameters.

53. The tester of claim 49, wherein during a READ operation the one or more delay elements delay the at least one timing signal to the tester logic relative to read data received from the device under test.

54. The tester of claim 53, wherein the at least one timing signal received by the tester logic comprises a data strobe (DQS) signal.

55. The tester of claim 44, wherein the tester logic further comprises:

a clock generator that generates at least one clock signal received by the tester logic and at least one timing signal that coordinates data transfer between the tester logic and the at least one device under test; and

one or more delay elements that selectively alter the phase of data signals communicated between the at least one device under test and the tester logic to test timing sensitivity of the at least one device under test.

56. The tester of claim 55, wherein the at least one timing signal is received by the at least one device tinder test from the tester logic and comprises a data strobe signal;

and

said tester logic includes one or more delay elements that during a WRITE operation selectively delay data signals received by the at least one device under test from the tester logic to test timing sensitivity of the at least one device under test for input hold and input setup timing parameters.

57. The tester of claim 55, wherein the at least one timing signal is received by the tester logic from the at least one die and comprises a data strobe signal;

and

said tester logic includes one or more delay elements that during a READ operation selectively delay data signals received by the tester logic from the at least one device under test to test timing sensitivity of the at least one device under test.

58. The tester of claim 49, wherein the one or more delay elements shift phases of both data signals and the at least one timing signal in small increments.

59. The tester of claim 58, wherein:

said tester further comprises a power subsystem including a variable reference voltage supply and variable supply voltage supply coupled to said wafer probe card to supply a reference voltage and a supply voltage to said at least one device under test through said connections; and

said tester logic comprises means for testing sensitivity of the device under test to timing and voltage combinations by setting the one or more delay elements to delay data strobe and data signals while setting at least one of the reference voltage and supply voltages outside of normal operating voltage ranges.

60. The tester of claim 59, wherein:

the test fixture comprises at least one variable impedance; and

the tester logic comprises means for varying the variable impedance to test sensitivity of said at least one device under test while testing with multiple combinations of timing signal and data delays and reference and supply voltages.

61. The tester of claim 44, wherein:

the at least one memory module comprises a memory device; and

the tester logic comprises a tester logic interface to which a host system communicates memory access requests in order to access the memory device.

62. The tester of claim 61, and further comprising the host system coupled to the tester logic interface, wherein the host system accesses the memory devices via the tester logic and fixture by communicating memory access requests to the tester logic interface.

63. A memory tester, comprising:

a connector having connections for a double data rate (DDR) memory device under test that is one of a memory die on a wafer, a packaged integrated circuit memory device and a memory module, wherein the connections of the connector present an impedance selected to emulate the characteristic impedance of an end-use environment for the at least device under test; and

tester logic, coupled to the apparatus, that communicates test data with the device under test.

64. The memory tester of claim 63, wherein the end-use environment is one of a DDR memory bus and a DDR memory module, and said characteristic impedance is approximately 60 ohms.

69. The memory tester of claim 63, and further comprising the memory device under test, wherein the memory device under test comprises a flash non-volatile memory with a synchronous DRAM-compatible memory interface.

65. A method of testing an integrated circuit device, said method comprising:

connecting to connections of a connector a memory device under test that is one of a double data rate (DDR) packaged integrated circuit memory device, a DDR memory die on a wafer, and a memory module, wherein the connections present an impedance selected to emulate the characteristic impedance of an end-use environment for the device under test; and

coupling test logic to the connector;

communicating test data between the device under test and the test logic via the connector to test the device under test.

66. A memory tester, comprising:

a test fixture having connections for a memory device under test that is one of a packaged integrated circuit memory device, a memory die on a wafer, and a memory module, wherein the connections present an impedance selected to emulate the characteristic impedance of an end-use environment for the device under test; and

;

tester logic including;

test circuitry for testing a plurality of types of memory devices;

a connector coupled to said test circuitry to enable connection of at least one of a plurality of different removable control modules; and

a removable control module coupled to said test circuitry via said connector that controls a device under test that is one of said plurality of types of memory devices.

67. A memory tester, comprising:

a test fixture having connections for at least one device under test that comprises one of a memory die on a wafer, a packaged integrated circuit memory device and a memory module, wherein the connections of the test fixture present an impedance selected to emulate the characteristic impedance of an end-use environment of the device under test; and

tester logic coupled to the test fixture, said tester logic including a memory controller and a packet protocol controller that communicates test data between the memory controller and the device under test via the test fixture utilizing framed packets.

68. A memory tester, comprising:

a test fixture having connections for at least one device under test that comprises one of a memory die on a wafer, a packaged integrated circuit memory device and a memory module, wherein the connections of the test fixture present an impedance selected to emulate the characteristic impedance of an end-use environment of the device under test;

a clock that supplies a clock signal to the device under test; and

tester logic coupled to the test fixture, said tester logic including a memory controller and a transfer circuit that communicates test data between the memory controller and the device under test via the test fixture at least twice a frequency of the clock signal.