Monocycle generator

• US 20030076136A1
• Filed: 09/04/2002
• Published: 04/24/2003
• Est. Priority Date: 09/04/2001
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: McCorkle, John W., Huynh, Phuong T., Ochoa, Agustin
• Granted Patent: US 7,030,663 B2
• Time in Patent Office: Days
• US Class Current: 327/112
• CPC Class Codes: G01S 7/282 Transmitters
• CPC Class Codes: H03K 5/05 by the use of clock signals or other time reference signals
• CPC Class Codes: H03K 5/151 with two complementary outputs
• CPC Class Codes: H03K 7/04 Position modulation, i.e. PPM
• CPC Class Codes: H04B 1/7174 Pulse generation in general H04L25/03834

Abstract

A monocycle forming network may include a monocycle generator, up and down pulse generators, data modulators and clock generation circuits. The network may generate monocycle pulses having very narrow pulse widths, approximately 80 picoseconds peak to peak. The monocycles may be modulated to carry data in ultra-wideband communication systems.

Claims

1. A monocycle generator, comprising:

a pair of transistors, a first transistor coupled to a first voltage source, a second transistor coupled to a second voltage source, both transistors coupled to a common output terminal, and

means for maintaining the output terminal at a voltage intermediate between the first and second voltages when the transistors are non-conductive.

2. The monocycle generator of claim 1, wherein the means comprises a voltage divider.

3. The monocycle generator of claim 1, wherein the means comprises a voltage regulator.

4. The monocycle generator of claim 1, further comprising:

a second pair of transistors, one coupled to the first voltage source, another coupled to the second voltage source, both coupled to a second output terminal,

wherein the means comprises a voltage divider coupling the first output terminal to the second output terminal and a reference potential coupled to a node within the voltage divider.

5. The monocycle generator of claim 1, further comprising:

a second pair of transistors, one coupled to the first voltage source, another coupled to the second voltage source, both coupled to a second output terminal,

wherein the means comprises a third pair of transistors bridging between the first and second output terminals and a reference potential coupled to a node between the third pair of transistors.

6. The monocycle generator of claim 1, further comprising third and fourth transistors, the third transistor coupling the means to the first voltage source and the fourth transistor coupling the means to the second voltage source.

7. The monocycle generator of claim 6, wherein inputs of the first and fourth transistors are coupled to a common signal source and the first and fourth transistors are of different device types.

8. The monocycle generator of claim 6, wherein inputs of the second and third transistors are coupled to a common signal source and the second and third transistors are of different device types.

9. The monocycle generator of claim 1, further comprising a down pulse generator coupled to an input of the first transistor, the down pulse generator comprising:

a pair of pull up transistors each bridging an input of the first transistor to the first voltage source,

an input of the first pull up transistor coupled to a first clock source,

an input of the second pull up transistor coupled to a second clock source that is

delayed and inverted with respect to first clock source,

a first pull down transistor bridging the input of the first transistor to the second voltage source,

a second pull down transistor bridging an input of the first pull down transistor to the second voltage source, an input of the second pull down transistor coupled to a third clock source that is delayed with respect to the first clock source,

a gate having an input coupled to the first clock source, an output coupled to the input of the first pull down transistor and a control input coupled to the second clock source.

10. The monocycle generator of claim 1, further comprising an up pulse generator coupled to an input of the second transistor, the up pulse generator comprising:

a pair of pull down transistors each bridging the input of the second transistor to the second voltage source,

the first pull down transistor coupled to a first clock source,

the second pull down transistor coupled to a second clock source that is delayed and inverted with respect to the first clock source,

a first pull up transistor bridging the input of the second transistor to the second voltage source,

a second pull up transistor bridging an input of the first pull up transistor to the second voltage source, an input of the second pull up transistor coupled to a third clock source that is delayed with respect to the first clock source,

a gate having an input coupled to the first clock source, an output coupled to the input of the first pull up transistor and a control input coupled to the third clock source.

11. The monocycle generator of claim 1, wherein the first and second transistors are conductive in response to an active portion of an up pulse signal.

12. The monocycle generator of claim 1, wherein the first potential source comprises:

a delay block having an input for a clock signal,

a phase detector having an input for the clock signal and a second input coupled to the delay block, and

a charge pump coupled to the phase detector having an output coupled to the first and third transistors and to the delay block.

13. A monocycle generator, comprising:

a pair of transistors, a first transistor coupled to a first voltage source, a second transistor coupled to a second voltage source, both transistors coupled to a common output terminal, and

a voltage divider coupled to the first and second voltage sources, a node of the voltage divider coupled to the output terminal.

14. The monocycle generator of claim 13, wherein the first and second transistors each are conductive in response to respective activation pulses and timing of the respective activation pulses is modulated to carry information.

15. A monocycle generator, comprising:

a pair of transistors, a first transistor coupled to a first voltage source, a second transistor coupled to a second voltage source, both transistors coupled to a common output terminal, and

a voltage regulator coupled to the first and second voltage sources to maintain the output terminal at a third potential when the first and second transistors are non-conductive.

16. The monocycle generator of claim 15, wherein the first and second transistors each are conductive in response to respective activation pulses and timing of the respective activation pulses is modulated to carry information.

17. A monocycle generator, comprising:

a pair of pull up transistors, each coupled to one of first and second output terminals and to a first voltage source,

a pair of pull down transistors, each coupled to one of the first and second output terminals and to a second voltage source,

a voltage divider coupled to the first and second output terminals,

a reference potential coupled to an interior node of the voltage divider.

18. The monocycle generator of claim 17, wherein:

the pull up transistor coupled to the first output terminal and the pull down transistor coupled to the second output terminal are conductive in response to a first set of activation pulses,

the pull up transistor coupled to the second output terminal and the pull down transistor coupled to the first output terminal are conductive in response to a second set of activation pulses, and

timing of the respective sets of activation pulse is modulated in response to an information signal.

19. A monocycle generator, comprising:

a pair of pull up transistors, each coupled to respective ones of first and second output terminals and to a first voltage source,

a pair of pull down transistors, each coupled to respective ones of the first and second output terminals and to a second voltage source,

a pair of transistors bridging between the first and second output terminals,

a reference potential coupled to a node between the two bridging transistors.

20. The monocycle generator of claim 19, wherein:

the pull up transistor coupled to the first output terminal and the pull down transistor coupled to the second output terminal are conductive in response to a first set of activation pulses,

the pull up transistor coupled to the second output terminal and the pull down transistor coupled to the first output terminal are conductive in response to a second set of activation pulses, and

timing of the respective sets of activation pulse is modulated in response to an information signal.

21. A transmitter, comprising:

a data modulator coupled to a clock source and having an input for a data signal,

a pair of pulse activators each coupled to the data modulator, and p1 a monocycle generator coupled to each of the pulse activators.

22. The transmitter of claim 21, wherein the pulse activators each generate activation pulses to the monocycle generator and timing between the activation pulses is modulated in response to an information signal.

23. The transmitter of claim 21, wherein the monocycle generator comprises:

a pair of transistors, a first transistor coupled to a first voltage source, a second transistor coupled to a second voltage source, and

a voltage divider, bridging between the first and second voltage sources, wherein the two transistors are coupled to a node within the voltage divider.

24. The transmitter of claim 21, wherein the monocycle generator comprises:

a pair of transistors, a first transistor coupled to a first voltage source, a second transistor coupled to a second voltage source, and

a voltage regulator, bridging between the first and second voltage sources, wherein the two transistors are coupled to a node within the voltage regulator.

25. The transmitter of claim 21, wherein the monocycle generator comprises:

a pair of pull up transistors, each coupled to respective ones of first and second output terminals and to a first voltage source,

a pair of pull down transistors, each coupled to respective ones of the first and second output terminals and to a second voltage source,

a voltage divider, coupled to the first and second output terminals,

a reference potential, coupled to an interior node of the voltage divider.

26. The transmitter of claim 21, wherein the monocycle generator comprises:

a pair of pull up transistors, each coupled to respective ones of first and second output terminals and to a first voltage source,

a pair of pull down transistors, each coupled to respective ones of the first and second output terminals and to a second voltage source,

a pair of transistors bridging between the first and second output terminals,

a reference potential, couple to a node between the two bridging transistors.

27. The transmitter of claim 21, wherein at least one pulse activator is a down pulse generator comprising:

an inverter coupled to the data modulator, and

a NAND gate having a first input coupled to the data modulator and a second input coupled to an output of the inverter.

28. The transmitter of claim 21, wherein at least one pulse activator is a down pulse generator comprising:

a cascaded chain of inverters, a first inverter coupled to the data modulator, and

a NAND gate having a first input coupled to the data modulator and a second input coupled to an output of a last inverter.

29. The transmitter of claim 21, wherein at least one pulse activator is a down pulse generator comprising:

an output terminal coupled to the monocycle generator,

a pair of pull up transistors each bridging the output terminal to a first potential source, the first pull up transistor coupled to the data modulator, the second pull up transistor coupled to

a first signal source that is delayed and inverted with respect to a signal output from the data modulator,

a first pull down transistor bridging the output terminal to a second potential source,

a second pull down transistor bridging an input of the first pull down transistor to the second potential source, an input of the second pull down transistor coupled to a second signal source that is delayed with respect to the signal output from the data modulator,

a gate, coupled to the data modulator, having an output that is coupled to the input of the first pull down transistor and having a control input coupled to the first signal source.

30. The transmitter of claim 21, wherein at least one pulse activator is an up pulse generator comprising:

an inverter coupled to the data modulator, and

a NOR gate having a first input coupled to the data modulator and a second input coupled to an output of the inverter.

31. The transmitter of claim 21, wherein at least one pulse activator is an up pulse generator comprising:

a cascaded series of inverters, a first inverter coupled to the data modulator, and

a NOR gate having a first input coupled to the data modulator and a second input coupled to an output of a last inverter.

32. The transmitter of claim 21, wherein at least one pulse activator is an up pulse generator comprising:

an output terminal coupled to the monocycle generator,

a pair of pull down transistors each bridging the output terminal to a first potential source, the first pull down transistor coupled to the data modulator, the second pull down transistor coupled to a first signal source that is delayed and inverted with respect to a signal from the data modulator,

a first pull up transistor bridging the output terminal to a second potential source,

a second pull up transistor bridging an input of the first pull up transistor to the second potential source, an input of the second pull up transistor coupled to a second signal source that is delayed with respect to the signal from the data modulator,

a gate, coupled to the data modulator, having an output that is coupled to the input of the first pull down transistor and having a control input coupled to the second signal source.

33. The transmitter of claim 21, wherein the data modulator comprises:

a delay block coupled to a clock source, and

four transmission gates, the first two transmission gates coupled to the clock source and the second two transmission gates coupled to the delay block, wherein;

the first and third transmission gates are coupled to the first pulse activator,

the second and fourth transmission gates are coupled to the second pulse activator,

the first and fourth transmission gates are rendered open in response to a first state of a data signal, and

the second and third transmission gates are rendered open in response to a second state of the data signal, the second state complementary to the first state.

34. The transmitter of claim 21, further comprising a second data modulator, wherein:

each data modulator comprises a fast path coupled to a source clock, and a slow path coupled to the source clock and comprising a delay block,

wherein the first data modulator is enabled in response to a first state of an input data signal and the second data modulator is enabled in response to a second state of the input data signal, the second state complementary to the first state.

35. A down pulse generator, comprising:

a pair of pull up transistors each bridging a common node to a first potential source, the first pull up transistor coupled to a first clock source, the second pull up transistor coupled to a second clock source that is delayed and inverted with respect to the first clock source,

a first pull down transistor bridging the common node to a second potential source,

a second pull down transistor bridging an input of the first pull down transistor to the second potential source, an input of the second pull down transistor coupled to a third clock source that is delayed with respect to the first clock source,

a gate having an input coupled to the first clock source, an output coupled to the input of the first pull down transistor and a control input coupled to the second clock source.

36. An up pulse generator, comprising:

a pair of pull down transistors each bridging a common node to a first potential source, the first pull down transistor coupled to a first clock source, the second pull down transistor coupled to a second clock source that is delayed and inverted with respect to the first clock source,

a first pull up transistor bridging the common node to a second potential source,

a second pull up transistor bridging an input of the first pull up transistor to the second potential source, an input of the second pull up transistor coupled to a third clock source that is delayed with respect to the first clock source,

a gate, having an input coupled to the first clock source, an output coupled to the input of the first pull up transistor and a control input coupled to the third clock source.

37. A skew controller, comprising:

a delay block having an input for a clock signal, the delay block imposing a one cycle delay to the clock signal,

a phase detector having an input for the clock signal and a second input coupled to the delay block, and

a charge pump coupled to the phase detector having an output coupled to the first and third transistors and to the delay block.

38. A monocycle pulse, generated according to a process of:

driving an output terminal to a first predetermined potential in response to a first pulse signal,

driving the output terminal to a second predetermined potential in response to a second pulse signal,

maintaining the output terminal at a third predetermined potential, intermediate between the first and second potentials, in the absence of the first and second pulse signals,

wherein a timing order between the first and second pulse signals is modulated in accordance with a data signal.

39. The monocycle pulse of claim 38, wherein an orientation of the monocycle pulse is determined by the timing order.

40. The monocycle pulse of claim 38, wherein the monocycle pulse has a peak-to-peak width of 80 picoseconds at most.

41. A monocycle pulse, generated according to a process of:

pulling an output terminal to a first predetermined potential in response to a first pulse signal,

pulling the output terminal to a second predetermined potential in response to a second pulse signal,

maintaining the output terminal at a third predetermined potential, intermediate between the first and second potentials, in the absence of the first and second pulse signals,

an orientation of the monocycle pulse is modulated to carry information.

42. The monocycle pulse of claim 41, wherein a timing order between the first and second pulse signals is modulated according to the information.

43. The monocycle pulse of claim 41, wherein the monocycle pulse has a peak-to-peak width of 80 picoseconds at most.

44. A method of generating a monocycle pulse, comprising:

driving an output terminal to a first predetermined potential in response to a first pulse activation signal,

driving the output terminal to a second predetermined potential in response to a second pulse signal,

maintaining the output terminal at a third predetermined potential, intermediate between the first and second potentials, in the absence of the first and second pulse signals,

wherein a timing order between the first and second pulse signals is modulated in accordance with a data signal.

45. The method of claim 44, wherein the first pulse signal is a down pulse and the second pulse signal is an up pulse.

46. The method of claim 44, wherein the first and second pulse signals both are up pulses.

47. The method of claim 44, wherein the first and second pulse signals both are down pulses.