Low Jitter ring oscillator architecture

• US 20030076179A1
• Filed: 08/07/2002
• Published: 04/24/2003
• Est. Priority Date: 09/07/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Branch, Charles M., Gata, Daramana, Fang, Lieyi, Hochschild, James R.
• Granted Patent: US 6,650,191 B2
• Time in Patent Office: Days
• US Class Current: 331/57
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/0322 with differential cells

Abstract

A low power and low jitter CMOS ring oscillator having a novel architecture that includes fully symmetrical differential current steering delay cells. This novel ring oscillator includes a first capacitor coupled between the first power supply rail and a bias voltage input. At least one stage couples across the first capacitor. Each stage includes a first transistor, a second capacitor, and a fully symmetrical differential delay cell. In an embodiment, the first transistor may be a PMOS transistor, where the drain of the first PMOS transistor connects to the first power supply rail and the gate of the first PMOS transistor couple to the bias voltage input. The second capacitor couples between the source of the first transistor and ground and acts as a low pass filter. As a result, the second capacitor minimizes the effects of the thermal and flicker noise of the devices which provide the tail current. The fully symmetrical differential delay cell includes a control input, a differential input and a differential output. The control input couples to the source of the first PMOS transistor. When one stage is present, the differential input couples to the differential output. When more than one stage is present, the differential outputs couple to the differential inputs of the concurrent delay cell. In addition, the delay cell in the last stage couples to the differential input of the delay cell in the first stage.

Claims

1. A ring oscillator, having a first, second, and third power supply rail, comprising:

a first capacitor coupled between the first power supply rail and the bias voltage input; and

at least one stage coupled across the first capacitor comprising,

a first transistor having a gate, a drain, and a source, the drain coupled to the first power supply, the gate coupled to the bias voltage input,

a second capacitor coupled between the source of the first transistor and the third power supply rail, and

a fully symmetrical differential delay cell, having a control input, a differential input and a differential output, the source of the first transistor coupled to the control input to apply a supply voltage,

wherein, when one stage is present, the differential inputs couple to the differential outputs,

wherein, when more than one stage is present such that a first and a last stage exists, the differential outputs of each delay cell coupled to the differential inputs of the delay cell in the concurrent stage, and the differential outputs of the delay cell in the last stage couples to the differential inputs of the delay cell in the first stage.

2. A ring oscillator as recited in claim 1, wherein the first transistor is a PMOS transistor and the third power supply rail is ground.

3. A ring oscillator as recited in claim 1, wherein the first transistor is a NMOS transistor and the first and third power supply rails are ground.

4. A ring oscillator as recited in claim 1 wherein the fully symmetrical differential delay cell comprises,

a current source coupled to the first power supply rail;

a first input circuit including a second and third transistor, each transistor having a respective gate, source and drain, each gate coupled to the first differential input, the source of the second transistor coupled to the current source, the source of the third transistor coupled to the third power supply rail;

a second input circuit including a fourth and fifth transistor, each transistor having a respective gate, source and drain, each gate coupled to the first differential input, the source of the fourth transistor coupled to the current source, the source of the fifth transistor coupled to the third power supply rail, the drain of the fourth transistor coupled to the drain of the fifth transistor;

a first output circuit having a first common node coupled to the first differential output, the first output circuit including two diodes coupled in series between the current source and the third power supply rail, the respective drains of the second and third transistor couple to the first common node; and

a second output circuit having a second common node coupled to the second differential output, the second output circuit including two diodes coupled in series between the current source and the third power supply rail, the respective drains of the fourth and fifth transistor couple to the second common node.

5. A ring oscillator as recited in claim 1 wherein the fully symmetrical differential delay cell comprises,

a current source coupled to the first power supply line;

a second transistor, having a gate, a drain, and a source, the drain coupled to the current source;

a third transistor, having a gate, a drain, and a source, the drain coupled to the current source, the source coupled to the source of the second transistor, the gate coupled to the source to form a first differential output;

a fourth transistor, having a gate, a drain, and a source, the gate coupled to the gate of the second transistor to form a first differential input, the source coupled to the first differential output, the drain coupled to the third power supply rail;

a fifth transistor, having a gate, a drain, and a source, the source coupled to the first differential output, the gate coupled to the first differential output, the drain coupled to the third power supply rail;

a sixth transistor, having a gate, a drain, and a source, the drain coupled to the current source, the gate coupled to the source to form a second differential output;

a seventh transistor, having a gate, a drain, and a source, the drain coupled to the current source;

a eighth transistor, having a gate, a drain, and a source, the source coupled to the second differential output, the gate coupled to the source, the drain coupled to the third power supply rail; and

a ninth transistor, having a gate, a drain, and a source, the gate coupled to the gate of the seventh transistor to form a second differential input, the source coupled to the second differential output, the drain coupled to the third power supply rail.

6. A phase locked loop, having an input and an output, comprising:

a first frequency divider coupled to the input;

a comparator coupled to the first frequency divider;

a filter coupled to the comparator;

a ring oscillator, having a first, second and third power supply rail, the ring oscillator coupled between the filter and the output, the ring oscillator comprising,

a first capacitor, and

at least one stage coupled across the first capacitor comprising,

a first transistor having a gate, a drain, and a source, the drain coupled to the first power supply, the gate coupled to the bias voltage input,

a second capacitor coupled between the source of the first transistor and the third power supply rail, and

a fully symmetrical differential delay cell coupled to the source of the first transistor; and

a second frequency divider coupled between the ring oscillator and the comparator to provide feedback.