Novel structure to reduce the degradation of the Q value of an inductor caused by via resistance

• US 20030076209A1
• Filed: 09/10/2001
• Published: 04/24/2003
• Est. Priority Date: 09/10/2001
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wong, Shyh-Chyi, Tsai, Chao Chieh
• Granted Patent: US 6,636,139 B2
• Time in Patent Office: Days
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind

Abstract

A new method and structure is provided to connect a planar, spiral inductor to underlying interconnect metal, the interconnect metal has been created over a semiconductor surface. A layer of dielectric followed by a layer of passivation is deposited over the semiconductor surface, including the surface of the underlying interconnect metal. Large first vias are created through the layers of passivation and dielectric. The large first vias align with the patterned interconnect metal, providing low-resistivity points of interconnect between the spiral inductor, which is created on the surface of the layer of passivation concurrent with the creation of the large first vias, and the patterned interconnect metal. A thick layer of polyimide is deposited over the surface of the layer of passivation, including the surface of the spiral inductor and the large first vias. The invention can further be extended by creating at least one second via through the thick layer of polyimide aligned with at least one of the created first vias. A patterned and etched layer of metal that fills the second via creates a re-distribution layer on the surface of the thick layer of polyimide for flip chip interconnects.

Claims

1. A method of creating a spiral inductor, comprising the steps of:

providing a substrate, interconnect lines having been provided over the surface of said substrate for connection thereto of inductor terminals;

depositing a layer of dielectric over the surface of said substrate, thereby including the surface of said interconnect line;

depositing a layer of passivation over the surface of said layer of dielectric;

patterning and etching said layer of dielectric and said layer of passivation, creating first via openings through said layers of dielectric and passivation that are aligned with said interconnect lines provided over the surface of said substrate, exposing the surface of said interconnect lines;

depositing a first layer of metal over the surface of said layer of passivation, including inside surfaces of said first via openings created through said layers of passivation and dielectric, said first layer of metal being deposited to a thickness between about 6 and 26 μ

m;

patterning and etching said deposited first layer of metal, creating metal lines for an inductor, further creating first vias for interconnecting said inductor to said exposed surfaces of said interconnect lines, said first vias being connected to said inductor and forming terminal ports for said inductor; and

depositing a thick layer of polyimide over the surface of said layer of passivation, including the surface of said created inductor and inside surfaces of said created first vias.

2. The method of claim 1 wherein said thick layer of polyimide is deposited to a thickness between about 30 and 60 μ

m.

3. The method of claim 1 wherein said first via has a surface area overlying said layer of passivation of about 7×

7 μ

m for application at higher level metal.

4. The method of claim 1 wherein said first via has a surface area overlying said layer of passivation larger than about 7×

7 μ

m for application at higher level metal.

5. The method of claim 1 wherein said first layer of metal is deposited using plating or screen printing techniques.

6. The method of claim 1 wherein said first layer of metal comprises a material selected from the group consisting of gold and copper and platinum.

7. The method of claim 1 wherein said first via has a smallest surface area overlying said layer of passivation of about 0.17×

0.17 μ

m, said surface area of said first via overlying said layer of passivation can exceed said smallest surface area by a measurable amount.

8. The method of claim 1 with additional step of:

creating at least one opening through said thick layer of polyimide, said at least one opening being aligned with at least one of said first vias created for interconnecting said inductor to said exposed surfaces of said interconnect lines;

depositing a second layer of metal over the surface of said thick layer of polyimide, including inside surfaces of said at least one opening created through said thick layer of polyimide, said second layer of metal being deposited to a thickness between about 6 and 26 μ

m; and

patterning and etching said second layer of metal, creating at least one second via being aligned with at least one of said first vias created for interconnecting said inductor to said exposed surfaces of said interconnect lines, providing a re-distribution layer on the surface of said thick layer of polyimide for flip chip interconnects.

9. The method of claim 8 wherein said second via has a surface area overlying said layer of polyimide of about 7×

7 μ

m.

10. The method of claim 8 wherein said second via has a surface area overlying said layer of polyimide larger than about 7×

7 μ

m.

11. The method of claim 8 wherein said second layer of metal is deposited using plating or screen printing techniques.

12. The method of claim 8 wherein said second layer of metal comprises a material selected from the group consisting of gold and copper and platinum.

13. The method of claim 8 wherein said second via has a smallest surface area overlying said layer of polyimide of about 0.17×

0.17 μ

m for application at lower level metal, said surface area of said second via overlying said layer of polyimide can exceed said smallest surface area by a measurable amount.

19. The structure of claim 1, said first via having a smallest surface area overlying said layer of passivation of about 0.17×

0.17 μ

m for application at lower level metal, said surface area of said first via overlying said layer of passivation can exceed said smallest surface area by a measurable amount.

14. The structure of a spiral inductor, comprising:

a substrate, interconnect lines having been provided over the surface of said substrate for connection thereto of inductor terminals;

a layer of dielectric deposited over the surface of said substrate, thereby including the surface of said interconnect line;

a layer of passivation deposited over the surface of said layer of dielectric;

first via openings created through said layers of dielectric and passivation that are aligned with said interconnect lines provided on the surface of said substrate, exposing the surface of said interconnect lines, said first via openings being created large enough for the deposition of a layer of metal with a thickness between about 6 and 26 μ

m over inside surfaces of said first vias;

a first layer of metal deposited over the surface of said layer of passivation, including inside surface of said first via openings created through said layers of passivation and dielectric, said first layer of metal being deposited to a thickness between about 6 and 26 μ

m;

said deposited first layer of metal having been patterned and etched, creating metal lines for an inductor, further creating first vias for interconnect said inductor to said exposed surfaces of said interconnect lines, said first vias being connected to said inductor and forming terminal ports for said inductor; and

a thick layer of polyimide deposited over the surface of said layer of passivation, including the surface of said created inductor and inside surfaces of said created first vias.

15. The structure of claim 14, said thick layer of polyimide having a thickness between about 30 and 60 μ

m.

16. The structure of claim 14, said first via having a surface area overlying said layer of passivation of about 7×

7 μ

m.

17. The structure of claim 14, said first via having a surface area overlying said layer of passivation larger than about 7×

7 μ

m.

18. The structure of claim 14, said first layer of metal comprising a material selected from the group consisting of gold and copper and platinum.

20. The structure of claim 14 with the addition of:

at least one opening created through said thick layer of polyimide, said at least one opening being aligned with at least one of said first vias created for interconnecting said inductor to said exposed surfaces of said interconnect lines;

a second layer of metal deposited over the surface of said thick layer of polyimide, including inside surfaces of said at least one opening created through said thick layer of polyimide, said second layer of metal being deposited to a thickness between about 6 and 26 μ

m; and

at least one second via created through said thick layer of polyimide being aligned with at least one of said first vias created for interconnecting said inductor to said exposed surfaces of said interconnect lines, providing a re-distribution layer on the surface of said thick layer of polyimide for flip chip interconnects.

21. The structure of claim 20, said second via having a surface area overlying said layer of polyimide of about 7×

7 μ

m.

22. The structure of claim 20, said second via having a surface area overlying said layer of polyimide larger than about 7×

7 μ

m.

23. The structure of claim 20, said second layer of metal being selected from the group consisting of gold and copper and platinum.

24. The structure of claim 20, said second via having a smallest surface area overlying said layer of polyimide of about 0.17×

0.17 μ

m for application at lower level metal, said surface area of said second via overlying said layer of polyimide can exceed said smallest surface area by a measurable amount.