Integrated circuit and manufacturing method therefor

• US 20030077845A1
• Filed: 10/17/2002
• Published: 04/24/2003
• Est. Priority Date: 10/19/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Ohkubo, Hiroaki, Nakashiba, Yasutaka
• Granted Patent: US 6,707,116 B2
• Time in Patent Office: Days
• US Class Current: 438/3
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind

Abstract

An integrated circuit is manufactured by providing a P⁻ or P⁻⁻ type semiconductor substrate with a resistivity of 10 to 1000 Ω·cm, disposing a CMOS on top of the semiconductor substrate, depositing an insulating film with several wirings embedded therein over the CMOS, and disposing an inductor on top of the insulating film in a region that is apart from where the CMOS is positioned. A p⁺ type diffused layer with a resistivity of about 0.01 Ω·cm is disposed between the semiconductor substrate and the CMOS.

Claims

1. An integrated circuit comprising:

a semiconductor substrate of a first conductivity type having an active device region and an inductor region that is apart from said active device region;

a semiconductor layer of said first conductivity type disposed on said semiconductor substrate, said semiconductor layer having a lower resistivity than said semiconductor substrate;

an active device disposed on a surface of said semiconductor layer in said active device region;

an insulating film disposed on said semiconductor layer so as to cover said active device;

an inductor disposed on said insulating film in said inductor region; and

a first layer of the first conductivity type locally disposed between said semiconductor layer and said semiconductor substrate in said active device region, said first layer having a lower resistivity than said semiconductor layer.

2. The integrated circuit according to claim 1, wherein said semiconductor substrate has a resistivity of 10 Ω

·

cm or higher.

3. The integrated circuit according to claim 1, wherein said first layer has a resistivity of 0.3 Ω

·

cm or lower.

4. An integrated circuit according to claim 1, further comprising a second layer of the first conductivity type locally disposed between said semiconductor layer and said semiconductor substrate in said inductor region, said second layer having a resistivity lower than that of said semiconductor layer but higher than that of said first layer.

5. The integrated circuit according to claim 4, wherein said second layer, when viewed along the direction perpendicular to the surface of said semiconductor substrate, is configured as a lattice.

6. The integrated circuit according to claim 4, wherein said second layer consists of a plurality of strip-shaped parts that are radially arranged when viewed along the direction perpendicular to the surface of said semiconductor substrate.

7. The integrated circuit according to claim 4, wherein said second layer consists of a plurality of strip-shaped parts that are arranged parallel to one another when viewed along the direction perpendicular to the surface of said semiconductor substrate.

8. The integrated circuit according to claim 4, wherein said semiconductor substrate has a resistivity of 10 Ω

·

cm or higher.

9. The integrated circuit according to claim 4, wherein said first layer has a resistivity of 0.3 Ω

·

cm or lower.

10. A manufacturing method for an integrated circuit, comprising the steps of:

locally forming a first layer of a first conductivity type on a semiconductor substrate of the first conductivity type in an active device region of said semiconductor substrate, said first layer having a lower resistivity than said semiconductor substrate;

depositing a semiconductor layer of the first conductivity type over said semiconductor substrate and said first layer, said semiconductor layer having a resistivity lower than that of said semiconductor substrate but higher than that of said first layer;

disposing an active device on the surface of said semiconductor layer in an active device region;

depositing an insulating film over said active device; and

disposing an inductor on said insulating film in an inductor region that is apart from said active device region.

11. The manufacturing method for an integrated circuit according to claim 10, wherein said first layer is formed by doping the surface of said semiconductor substrate with impurities.

12. The manufacturing method for an integrated circuit according to claim 10, wherein said first layer is formed by depositing a film on said semiconductor substrate using an epitaxy technique.

16. The manufacturing method for an integrated circuit according to claim 10, wherein said semiconductor substrate has a resistivity of 10 Ω

·

cm or higher.

17. The manufacturing method for an integrated circuit according to claim 10, wherein said first layer has a resistivity of 0.3 Ω

·

cm or lower.

13. A manufacturing method for an integrated circuit, comprising the steps of:

forming a second layer of a first conductivity type on a semiconductor substrate of the first conductivity type, said second layer having a lower resistivity than said semiconductor substrate;

locally implanting impurities of the first conductivity type into an active device region of said second layer to cause a part of said second layer to become a first layer of the first conductivity type, said first layer having a lower resistivity than said second layer;

depositing a semiconductor layer of the first conductivity type over said first layer and said second layer, said semiconductor layer having a resistivity lower than that of said semiconductor substrate but higher than that of said second layer;

disposing an active device on the surface of said semiconductor layer in said active device region;

depositing an insulating film over said active device; and

disposing an inductor on said insulating film in an inductor region of said second layer that is apart from said active device region.

14. The manufacturing method for an integrated circuit according to claim 13, wherein said first layer is formed by doping the surface of said semiconductor substrate with impurities.

15. The manufacturing method for an integrated circuit according to claim 13, wherein said first layer is formed by depositing a film on said semiconductor substrate using an epitaxy technique.