Fabrication of on-package and on-chip structure using build-up layer process

• US 20030077871A1
• Filed: 09/17/2002
• Published: 04/24/2003
• Est. Priority Date: 10/24/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ma, Qing, Cheng, Peng
• Granted Patent: US 6,890,829 B2
• Time in Patent Office: Days
• US Class Current: 438/381
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate

Abstract

The invention relates to a process of forming an on-chip package inductor. The process includes providing a substrate with at least one microelectronic device packaged therewith. As part of the inventive process, electrical communication is formed for the microelectronic device. The electrical communication includes at least two electrically conductive layers. As part of the inventive technology, the inductor is patterned on the substrate before, during, or after formation of the electrical communication. The inductor is connected to the at least one microelectronic device.

Claims

1. A process of forming an inductor comprising:

providing a substrate, wherein the substrate comprises at least one microelectronic device packaged therewith;

forming electrical communication for the at least one microelectronic device, wherein the electrical communication comprises at least two electrically conductive layers;

patterning an inductor on the substrate; and

connecting the inductor to the at least one microelectronic device.

2. The process according to claim 1, wherein providing a substrate comprises:

providing a first encapsulated device assembly, the first encapsulated device assembly having an active front surface, an inactive front surface, and a back surface.

3. The process according to claim 1, wherein patterning an inductor on the substrate comprises:

masking the active front surface of the first encapsulated device assembly during patterning of the inductor.

4. The process according to claim 1, wherein patterning an inductor on the substrate comprises:

forming an inductor simultaneously while forming the electrical communication.

5. The process according to claim 1, wherein patterning an inductor on the substrate comprises:

forming an inductor simultaneously while forming the electrical communication, wherein the inductor is made from at least two electrically conductive layers, and wherein at least one of the at least two electrically conductive layers is common to the electrical communication and the inductor.

6. The process according to claim 1, wherein patterning an inductor on the substrate comprises:

forming an inductor on the inactive front surface.

7. The process according to claim 1, wherein patterning an inductor on the substrate comprises:

forming a helical structure comprising at least two layers of electrically conductive material.

8. The process according to claim 1, wherein patterning an inductor on the substrate comprises:

forming a substantially two-dimensional, spiral structure.

9. The process according to claim 1, wherein patterning an inductor on the substrate comprises:

forming first helical coil; and

forming a second helical coil that is interwound with the first helical coil.

10. The process according to claim 1, wherein patterning an inductor on the substrate comprises:

forming first spiral coil with a first spiral direction.

11. The process according to claim 1, wherein patterning an inductor on the substrate comprises:

forming first spiral coil with a first spiral direction; and

forming a second coil with a second spiral direction that is wound opposite the first spiral direction.

12. The process according to claim 1, wherein patterning an inductor on the substrate comprises:

forming a first dielectric layer on the substrate;

patterning a first seed layer on the substrate;

patterning a first conductive trace on the first seed layer;

forming a second dielectric layer over the first conductive trace;

patterning a second seed layer on the second dielectric layer; and

patterning a second conductive trace over the second seed layer.

13. A process of forming an inductor comprising:

providing a substrate, wherein the substrate comprises at least one microelectronic device packaged therewith;

forming a first dielectric layer on the substrate;

patterning a first seed layer on the substrate;

patterning a first conductive trace on the first seed layer;

forming a second dielectric layer over the first conductive trace;

patterning a second seed layer on the second dielectric layer; and

patterning a second conductive trace over the second seed layer.

14. The process according to claim 13, wherein providing a substrate comprises:

providing the first encapsulated microelectronic device assembly with an active front surface, an inactive front surface, and a back surface.

15. The process according to claim 13, further comprising:

masking the active front surface of the first encapsulated device assembly during forming the inductor.

16. The process according to claim 14, further comprising:

forming electrical communication of the front active surface; and

forming the inductor simultaneously while forming the electrical communication.

17. The process according to claim 14, further comprising:

forming electrical communication on the front active surface;

forming the inductor simultaneously while forming the electrical communication, wherein the inductor is made from at least two electrically conductive layers, and wherein at least one of the at least two electrically conductive layers is common to the electrical communication and the inductor.

18. The process according to claim 14, wherein forming an inductor further comprises:

forming a helical structure comprising at least two layers of electrically conductive material, wherein the at least two layers of electrically conductive material comprise the first conductive trace and the second conductive trace.

19. The process according to claim 13, wherein forming an inductor further comprises:

forming a substantially two-dimensional, spiral structure, comprising at least two layers of electrically conductive material, wherein the at least two layers of electrically conductive material comprise the first conductive trace and the second conductive trace.

20. The process according to claim 13, wherein forming an inductor further comprises:

forming first helical coil; and

forming a second helical coil that is interwound with the first helical coil.

21. The process according to claim 13, wherein forming an inductor further comprises:

forming a first spiral coil.

22. The process according to claim 13, wherein forming an inductor further comprises:

forming a first spiral coil; and

forming a second spiral coil that winds opposite the first coil.

23. A process of forming an inductor comprising:

providing a substrate, wherein the substrate comprises at least one microelectronic device packaged therewith;

forming electrical communication for the at least one microelectronic device;

forming a first dielectric layer on the substrate;

patterning a first conductive trace over the first dielectric layer;

forming a second dielectric layer over the first conductive trace; and

patterning a second conductive trace over the second conductive trace; and

connecting the inductor to the at least one microelectronic device.

24. The process according to claim 23, further comprising:

before patterning a first conductive layer, patterning a first seed layer on the substrate; and

before patterning a second conductive layer, patterning a second seed layer on the second dielectric layer.

25. The process according to claim 23, wherein patterning comprises using lift-off technique.

26. The process according to claim 23, wherein providing a substrate comprises:

providing the first encapsulated microelectronic device assembly with an active front surface, an inactive front surface, and a back surface, wherein the inductor is disposed at a border of the active front surface and the inactive front surface.

27. The process according to claim 23, wherein providing a substrate comprises:

providing the first encapsulated microelectronic device assembly with an active front surface, an inactive front surface, and a back surface, wherein the inductor is disposed at a border of the active front surface and the inactive front surface; and

further comprising;

providing a back side inductor on the back surface.

28. A process of making an inductor package comprising:

forming an inductor upon a first substrate having an inactive surface;

providing a device comprising an active surface over a second substrate; and

flip-chip connecting the inductor to the device.

29. The process according to claim 28, wherein providing a device comprising an active surface further comprises:

providing the second substrate, wherein the second substrate comprises at least one microelectronic device packaged therewith;

forming electrical communication for the at least one microelectronic device; and

patterning an inductor on the second substrate.

30. The process according to claim 28, wherein providing a device comprising an active surface further comprises:

providing the second substrate, wherein the second substrate comprises at least one microelectronic device packaged therewith;

forming electrical communication for the at least one microelectronic device; and

patterning an inductor on the second substrate, wherein the inductor on the second substrate is disposed above the active surface.