Data control device and an ATM control device

• US 20030079091A1
• Filed: 11/12/2002
• Published: 04/24/2003
• Est. Priority Date: 05/12/2000
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Nakano, Masao, Ooba, Yasuhiro, Toyoyama, Takeshi
• Granted Patent: US 6,895,473 B2
• Time in Patent Office: Days
• US Class Current: 711/143
• CPC Class Codes: H04L 2012/5625 Operations, administration and maintenance [OAM]
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A data control device capable of high-quality, high-efficiency control for speeding up data processing, thus permitting improvement of the throughput of a system. Attribute analyzing unit analyzes an attribute of data, and a main memory stores setting information of the data in a region corresponding to the attribute. A highway cache memory stores the data, and also receives and transmits the data on a highway. A processor performs an operation on the data in accordance with the setting information. A data cache memory is interposed between the processor and the main memory and stores the setting information.

Claims

1. A data control device for controlling operations on data, comprising:

attribute analyzing means for analyzing an attribute of data;

a main memory for storing setting information of the data in a region corresponding to the attribute; and

a plurality of data processing means each including a highway cache memory for storing the data, said highway cache memory receiving and transmitting the data on a highway, a processor for performing an operation on the data in accordance with the setting information, and a data cache memory interposed between said processor and said main memory and storing the setting information, said plurality of data processing means subjecting the data to a plurality of stages of pipeline processing.

2. The data control device according to claim 1, wherein said data cache memory includes read means for reading the setting information from said main memory and storing the setting information, operation information storage means accessed by said processor and storing the setting information and a result of operation, and write-back means for writing the operation result back into said main memory as the setting information, and

said read means, said operation information storage means and said write-back means perform parallel processing independently of one another.

3. The data control device according to claim 2, wherein, when an operation is performed at a time t in each of said plurality of stages, said data cache memory executes the process of said operation information storage means, the read process for the setting information to be subjected to an operation at a time (t+1 stage processing time) and the write-back process for the setting information obtained by the operation at a time (t−

1 stage processing time) in parallel with one another.

4. The data control device according to claim 2, wherein, when an operation is performed at a time t in an Nth (N<

1) stage of said plurality of stages, said data cache memory of the Nth stage executes the process of said operation information storage means, the read process for the setting information to be subjected to an operation at a time (t+N stage processing times) and the write-back process for the setting information obtained by the operation at a time (t−

1 stage processing time) in parallel with one another.

5. The data control device according to claim 4, wherein said data cache memory of an Nth (N≧

2) stage of said plurality of stages includes setting information storage means, and when an operation is performed at the time t in the Nth stage, said setting information storage means stores the setting information to be subjected to an operation at a time (t+1 stage processing time) through the setting information to be subjected to an operation at a time (t+(N−

1) stage processing times).

6. The data control device according to claim 2, wherein said data cache memories of said plurality of stages transmit and receive the necessary setting information therebetween, said data cache memory of a first stage executes a collective read process for the setting information, the process of said operation information storage means and the write-back process, and said data cache memories of second to Nth stages execute the process of said operation information storage means and the write-back process.

7. The data control device according to claim 6, wherein said data cache memories of said plurality of stages include setting information storage means for storing the setting information transmitted/received therebetween.

8. The data control device according to claim 2, wherein said data cache memories of said plurality of stages transmit and receive the necessary setting information therebetween, said data cache memory of a first stage executes a collective read process for the setting information and the process of said operation information storage means, said data cache memories of second to (N−

1)th stages execute the process of said operation information storage means, and said data cache memory of an Nth stage executes the process of said operation information storage means and the write-back process.

9. The data control device according to claim 8, wherein said data cache memories of said plurality of stages include setting information storage means for storing the setting information transmitted/received therebetween.

10. The data control device according to claim 1, wherein said main memory is provided for each of said plurality of stages independently of one another.

11. An ATM control device for controlling ATM communications, comprising:

attribute analyzing means for analyzing an attribute of a cell;

a main memory for storing setting information of the cell in a region corresponding to the attribute; and

a plurality of cell processing means each including a highway cache memory for storing the cell, said highway cache memory receiving and transmitting the cell on a highway, a processor for performing an operation on the cell in accordance with the setting information, and a cell cache memory interposed between said processor and said main memory and storing the setting information, said plurality of cell processing means subjecting the cell to a plurality of stages of pipeline processing.

12. The ATM control device according to claim 11, wherein said cell cache memory includes read means for reading the setting information from said main memory and storing the setting information, operation information storage means accessed by said processor and storing the setting information and a result of operation, and write-back means for writing the operation result back into said main memory as the setting information, and

said read means, said operation information storage means and said write-back means perform parallel processing independently of one another.

13. The ATM control device according to claim 12, wherein, when an operation is performed at a time t in each of said plurality of stages, said cell cache memory executes the process of said operation information storage means, the read process for the setting information to be subjected to an operation at a time (t+1 stage processing time) and the write-back process for the setting information obtained by the operation at a time (t−

1 stage processing time) in parallel with one another.

14. The ATM control device according to claim 12, wherein, when an operation is performed at a time t in an Nth (N≧

1) stage of said plurality of stages, said cell cache memory of the Nth stage executes the process of said operation information storage means, the read process for the setting information to be subjected to an operation at a time (t+N stage processing times) and the write-back process for the setting information obtained by the operation at a time (t−

1 stage processing time) in parallel with one another.

15. The ATM control device according to claim 14, wherein said cell cache memory of an Nth (N≧

2) stage of said plurality of stages includes setting information storage means, and when an operation is performed at the time t in the Nth stage, said setting information storage means stores the setting information to be subjected to an operation at a time (t+1 stage processing time) through the setting information to be subjected to an operation at a time (t+(N−

1) stage processing times).

16. The ATM control device according to claim 12, wherein said cell cache memories of said plurality of stages transmit and receive the necessary setting information therebetween, said cell cache memory of a first stage executes a collective read process for the setting information, the process of said operation information storage means and the write-back process, and said cell cache memories of second to Nth stages execute the process of said operation information storage means and the write-back process.

17. The ATM control device according to claim 16, wherein said cell cache memories of said plurality of stages include setting information storage means for storing the setting information transmitted/received therebetween.

18. The ATM control device according to claim 12, wherein said cell cache memories of said plurality of stages transmit and receive the necessary setting information therebetween, said cell cache memory of a first stage executes a collective read process for the setting information and the process of said operation information storage means, said cell cache memories of second to (N−

1)th stages execute the process of said operation information storage means, and said cell cache memory of an Nth stage executes the process of said operation information storage means and the write-back process.

19. The ATM control device according to claim 18, wherein said cell cache memories of said plurality of stages include setting information storage means for storing the setting information transmitted/received therebetween.

20. The ATM control device according to claim 11, wherein said main memory is provided for each of said plurality of stages independently of one another.