Semiconductor device and method of manufacturing the same

• US 20030080375A1
• Filed: 04/29/2002
• Published: 05/01/2003
• Est. Priority Date: 10/30/2001
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki, Aono, Shinji
• Granted Patent: US 6,909,142 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N⁻-type silicon substrate (1). An N⁺-type impurity implantation region (4) is formed in an upper surface (3) of the N⁻-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N⁺-type impurity implantation region (4) is formed in the upper surface (3) of the N⁻-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N⁻-type silicon substrate (1). The aluminum electrode (8) is provided in contact with an upper surface of the polysilicon film (7) and the upper surface (3) of the N⁻-type silicon substrate (1). The aluminum electrode (8) is extended over the silicon oxide film (2) to constitute a field plate.

Claims

1. A semiconductor device comprising:

an N-type semiconductor substrate;

a transistor having a first P-type impurity introduced region formed in a main surface of said semiconductor substrate and constituting a main junction together with said semiconductor substrate; and

a channel stop structure formed in a peripheral portion of said semiconductor substrate,

wherein said channel stop structure has a first trench formed in said main surface of said semiconductor substrate.

2. The semiconductor device according to claim 1, wherein said channel stop structure further has a second N-type impurity introduced region formed in said main surface of said semiconductor substrate in a portion where said first trench is formed.

3. The semiconductor device according to claim 1, wherein said channel stop structure further has:

a first insulating film formed on an inner wall of said first trench; and

a first conductive film formed to fill in said first trench.

4. The semiconductor device according to claim 3, wherein said channel stop structure further has a second conductive film formed on said main surface of said semiconductor substrate through an insulating film, provided in contact with said first conductive film and said main surface of said semiconductor substrate and extended toward said main junction.

5. The semiconductor device according to claim 3, wherein a material of said first conductive film is polysilicon.

6. The semiconductor device according to claim 3, wherein said channel stop structure further has:

a second conductive film formed on said main surface of said semiconductor substrate through an insulating film, provided in contact with said first conductive film and said main surface of said semiconductor substrate and extended toward said main junction; and

a third conductive film formed on said second conductive film through an insulating film, provided in contact with said first conductive film and said main surface of said semiconductor substrate and extended toward said main junction.

7. The semiconductor device according to claim 3, wherein said transistor further has:

a third N-type impurity introduced region formed in said main surface of said semiconductor substrate and functioning as a source or an emitter of said transistor;

a second trench formed in said main surface of said semiconductor substrate in a portion where said third impurity introduced region is formed;

a second insulating film formed on an inner wall of said second trench and functioning as a gate insulating film of said transistor; and

a fourth conductive film formed to fill in said second trench and functioning as a gate electrode of said transistor, and wherein

said channel stop structure further has a fourth P-type impurity introduced region formed in said main surface of said semiconductor substrate.

8. The semiconductor device according to claim 7, wherein an opening width of said first trench is equal to that of said second trench.

9. The semiconductor device according to claim 7, wherein a material of said first conductive film is equal to that of said fourth conductive film.

10. A method of manufacturing a semiconductor device, comprising the steps of:

(a) preparing an N-type semiconductor substrate having a first region in which a transistor is to be formed and a second region in which a channel stop structure is to be formed;

(b) forming a first P-type impurity introduced region constituting a main junction together with said semiconductor substrate in a main surface of said semiconductor substrate in said first region; and

(c) forming a first trench in said main surface of said semiconductor substrate in said second region.

11. The method of manufacturing a semiconductor device according to claim 10, further comprising the step of:

(d) forming a second N-type impurity introduced region in said main surface of said semiconductor substrate in said second region.

12. The method of manufacturing a semiconductor device according to claim 10, further comprising the steps of:

(e) forming a first insulating film on an inner wall of said first trench; and

(f) forming a first conductive film to fill in said first trench after said step (e).

13. The method of manufacturing a semiconductor device according to claim 12, further comprising the step of:

(g) forming a second conductive film provided in contact with said first conductive film and said main surface of said semiconductor substrate and extended toward said main junction on said main surface of said semiconductor substrate in said second region through an insulating film.

14. The method of manufacturing a semiconductor device according to claim 12, further comprising the steps of:

(h) forming a third N-type impurity introduced region functioning as a source or an emitter of said transistor in said main surface of said semiconductor substrate in said first region;

(i) digging down a part of said main surface of said semiconductor substrate in a portion where said third impurity introduced region is provided, thereby forming a second trench;

(j) forming a second insulating film functioning as a gate insulating film of said transistor on an inner wall of said second trench;

(k) forming a fourth conductive film to fill in said second trench and to function as a gate electrode of said transistor after said step (j); and

(l) forming a fourth P-type impurity introduced region in said main surface of said semiconductor substrate in said second region.

15. The method of manufacturing a semiconductor device according to claim 14, wherein said steps (b) and (l) are executed in the same step.

16. The method of manufacturing a semiconductor device according to claim 14, wherein said steps (d) and (h) are executed in the same step.

17. The method of manufacturing a semiconductor device according to claim 14, wherein said steps (c) and (i) are executed in the same step.

18. The method of manufacturing a semiconductor device according to claim 14, wherein said steps (e) and (j) are executed in the same step.

19. The method of manufacturing a semiconductor device according to claim 14, wherein said steps (f) and (k) are executed in the same step.