Semiconductor component, trench structure transistor, trench MOSFET, IGBT, and field-plate transistor

• US 20030080378A1
• Filed: 10/29/2002
• Published: 05/01/2003
• Est. Priority Date: 10/29/2001
• Status: Active Grant

• Current Assignee: Franz Hirler, Markus Zundel
• Original Assignee: Franz Hirler, Markus Zundel
• Inventors: Hirler, Franz, Zundel, Markus
• Granted Patent: US 6,882,004 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/05042 Si3N4
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A semiconductor component has a minimal size and area requirement. The semiconductor component is formed in a trench with wall regions and a bottom region. Terminal regions for the electrical connection of first and second contact regions (S, B) are formed at least partly within the trench (30).

Claims

1. A semiconductor component, comprising:

a semiconductor substrate region having a trench with a width, wall regions, and a bottom region formed therein, said wall regions including an upper trench section;

a contact region formed outside and directly proximate said trench in a region of said upper trench section;

a terminal region for electrical connection of said contact region and formed at least partly within said trench; and

a trench side region being narrower than said width of said trench.

2. The semiconductor component according to claim 1, wherein:

said semiconductor substrate region has a further trench formed therein; and

said trench side region is a mesa region between said two trenches.

3. The semiconductor component according to claim 1, wherein:

said trench has a central trench section; and

a further contact region is formed outside said trench directly proximate said trench in a region of said central trench section.

4. The semiconductor component according to claim 3, further comprising a further terminal region for electrical connection of said further contact region formed at least partly within said trench.

5. The semiconductor component according to claim 4, wherein said terminal regions for said first and second contact regions are formed at least partly as a common terminal region.

6. The semiconductor component according to claim 5, wherein said terminal regions are formed within said trench.

7. The semiconductor component according to claim 4, further comprising a second semiconductor substrate within said trench and having a surface region, at least one of said terminal regions being formed with a depth of at least 50 nm from said surface region of said second semiconductor substrate.

8. The semiconductor component according to claim 3, wherein at least one of said contact region and said further contact region contact said wall region of said respective trench sections respectively.

9. The semiconductor component according to claim 4, wherein said terminal regions for said contact regions are formed at least in a region of said upper trench section.

10. The semiconductor component according to claim 5, wherein said common terminal region of said terminal regions is formed at least in a region of said upper trench section.

11. The semiconductor component according to claim 1, wherein said wall region has an upper wall section;

and

a contact between said contact region and said terminal region is disposed in a part of said upper wall section of said wall region of said trench.

12. The semiconductor component according to claim 5, wherein said wall region has an upper wall section;

and

a contact between said the first contact region and said common terminal region is disposed in a part of said upper wall section of said wall region of said trench.

13. The semiconductor component according to claim 11, wherein said contact is selected from the group consisting of a direct mechanical and electrical contact, a contact via a diffusion region, and a contact via an implantation region.

14. The semiconductor component according to claim 12, wherein said contact is selected from the group consisting of a direct mechanical and electrical contact, a contact via a diffusion region, and a contact via an implantation region.

15. The semiconductor component according to claim 9, wherein:

said wall region of said trench has an upper wall section; and

said first contact region forms at least a part of said upper wall section of said wall region of said trench.

16. The semiconductor component according to claim 10, wherein:

said wall region of said trench has an upper wall section; and

said first contact region forms at least a part of said upper wall section of said wall region of said trench.

17. The semiconductor component according to claim 11, wherein:

said wall region of said trench has an upper wall section; and

said first contact region forms at least a part of said upper wall section of said wall region of said trench.

18. The semiconductor component according to claim 12, wherein:

said wall region of said trench has an upper wall section; and

said first contact region forms at least a part of said upper wall section of said wall region of said trench.

19. The semiconductor component according to claim 3, wherein said further contact region is formed directly proximate said first contact region.

20. The semiconductor component according to claim 3, wherein said further contact region directly contacts said first contact region.

21. The semiconductor component according to claim 3, wherein:

said wall section of said trench has a central wall section; and

said further contact region forms at least a part of said central wall section of said wall region of said trench.

22. The semiconductor component according to claim 4, further comprising a contact of said further contact region contacting said further terminal region, said contact being formed via one of a diffusion region and an implantation region.

23. The semiconductor component according to claim 5, further comprising a contact of said further contact region contacting said common terminal region, said contact being formed via one of a diffusion region and an implantation region.

24. The semiconductor component as claimed in claim 22, wherein said one of a diffusion region and an implantation region for said contact connected to said second contact region is formed as a localized surface strip running transversely with respect to said trench.

25. The semiconductor component as claimed in claim 23, wherein said one of a diffusion region and an implantation region for said contact connected to said second contact region is formed as a localized surface strip running transversely with respect to said trench.

26. The semiconductor component according to claim 22, wherein said one of a diffusion region and an implantation region for said contact connected to said further contact region is formed as a surface region running longitudinally with respect to said trench.

27. The semiconductor component according to claim 26, wherein said surface region overlaps said contact region.

28. The semiconductor component according to claim 23, wherein said one of a diffusion region and an implantation region for said contact connected to said further contact region is formed as a surface region running longitudinally with respect to said trench.

29. The semiconductor component according to claim 28, wherein said surface region overlaps said contact region.

30. The semiconductor component according to claim 3, further comprising a second-further contact region is formed within said trench.

31. The semiconductor component according to claim 3, wherein said second-further contact region is formed at least partly within said trench in said region of said central trench section.

32. The semiconductor component according to claim 4, wherein:

said second-further contact region is formed at least partly within said trench in said region of said central trench section; and

at least one of an insulation region and an isolation oxide electrically insulates said second-further contact region from said contact region and said further contact region and from said terminal region and further terminal region.

33. The semiconductor component according to claim 5, wherein:

said second-further contact region is formed at least partly within said trench in said region of said central trench section; and

at least one of an insulation region and an isolation oxide electrically insulates said second-further contact region from said contact region and said further contact region and from said common terminal region.

34. The semiconductor component according to claim 30, further comprising a third-further contact region formed outside said trench directly proximate said trench in said region of said lower trench section.

38. The semiconductor component according to claim 34, wherein:

said contact region is a source region;

said further contact region is one of a body region and a substrate region;

said second-further contact region is a gate region; and

said third-further contact region is a drain region.

39. The semiconductor component according to claim 5, further comprising:

a second-further contact region is formed within said trench; and

a third-further contact region formed outside said trench directly proximate said trench in said region of said lower trench section;

said common terminal region is formed as a source-body terminal region;

said second-further contact region is a gate region; and

said third-further contact region is a drain region.

45. The semiconductor component according to claim 30, wherein said second-further contact region is formed within said trench.

46. The semiconductor component according to claim 45, wherein said second-further contact region is formed as a polysilicon region.

47. The semiconductor component according to claim 30, wherein a common terminal region for said contact region and second-further contact region is formed within the trench.

48. The semiconductor component according to claim 47, wherein said common terminal region is formed as a polysilicon region.

49. The semiconductor component according to claim 30, wherein at least one of said contact region and said second-further contact region are formed as conductivity regions having an inverted-U-shaped cross section.

50. The semiconductor component according to claim 49, wherein said contact region and said second-further contact region are disposed between adjacent semiconductor components.

51. The semiconductor component according to claim 49, wherein said inverted-U-shaped cross section has a U arc, said U-arc having an interruption.

52. The semiconductor component according to claim 51, wherein said inverted-U-shaped cross section has a mesa defined at a region proximate an adjacent semiconductor component, and said interruption is located in said mesa.

53. The semiconductor component according to claim 30, further comprising:

a terminal metallization; and

an insulation layer isolating said second-further contact region formed within said trench from said terminal metallization;

said terminal regions for said contact region and second-further contact region further isolating said second-further contact region from said terminal metallization.

54. The semiconductor component according to claim 53, wherein said insulating layer is an isolation oxide.

55. The semiconductor component according to claim 53, wherein said contact region and said second-further contact region are formed as a polysilicon region.

56. The semiconductor component according to claim 30, wherein said contact regions, said terminal regions, and said electrode regions are disposed within said trench and formed from a material selected from the group consisting of polysilicon, metal, and silicide.

57. The semiconductor component according to claim 56, wherein said contact regions, said terminal regions, said electrode regions have terminal regions for said contact region and said second-further contact region.

58. The semiconductor component according to claim 57, further comprising a terminal region for said second-further contact regions.

35. A trench structure transistor, comprising:

a semiconductor substrate region having a trench with a width, wall regions, and a bottom region formed therein, said wall regions including an upper trench section;

a contact region formed outside and directly proximate said trench in a region of said upper trench section;

a terminal region for electrical connection of said contact region and formed at least partly within said trench; and

a trench side region being narrower than said width of said trench.

36. A trench MOSFET, comprising:

a semiconductor substrate region having a trench with a width, wall regions, and a bottom region formed therein, said wall regions including an upper trench section;

a contact region formed outside and directly proximate said trench in a region of said upper trench section;

a terminal region for electrical connection of said contact region and formed at least partly within said trench; and

a trench side region being narrower than said width of said trench.

37. An IGBT, comprising:

a semiconductor substrate region having a trench with a width, wall regions, and a bottom region formed therein, said wall regions including an upper trench section;

a contact region formed outside and directly proximate said trench in a region of said upper trench section;

a terminal region for electrical connection of said contact region and formed at least partly within said trench; and

a trench side region being narrower than said width of said trench.

40. A field plate transistor, comprising:

a semiconductor substrate region having a trench with a width, wall regions, and a bottom region formed therein, said wall regions including an upper trench section;

a contact region formed outside and directly proximate said trench in a region of said upper trench section;

a terminal region for electrical connection of said contact region and formed at least partly within said trench; and

a trench side region being narrower than said width of said trench;

a second-further contact region is formed within said trench; and

a third-further contact region formed outside said trench directly proximate said trench in said region of said lower trench section.

41. The field plate transistor according to claim 40, further comprising:

a reinforced insulation region formed within at least one of said lower trench section, a transition region between said lower trench section and said central trench section between said semiconductor substrate region and said third contact region, said terminal regions for the first and third contact region, in particular the source and body contact regions.

42. The field plate transistor according to claim 41, wherein reinforced insulation region is a field plate.

43. The field plate transistor according to claim 41, wherein reinforced insulation region is a gate oxide formed within said trench.

44. The field plate transistor according to claim 41, wherein reinforced insulation region is a field oxide formed within said trench.