Integrated circuit having stress migration test structure and method therefor

• US 20030080766A1
• Filed: 10/31/2001
• Published: 05/01/2003
• Est. Priority Date: 10/31/2001
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Ryan, Vivian, Fetterman, H. Scott
• Granted Patent: US 6,683,465 B2
• Time in Patent Office: Days
• US Class Current: 324/763
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.

Claims

1. An integrated circuit, comprising:

a substrate having circuits fabricated thereon, the circuits connected to leads of the integrated circuit;

a stress migration test device fabricated on the substrate, the stress migration test device comprising a conductive runner, the conductive runner having a length sufficient to develop axial stress above the threshold for nucleating voids for the technology in which the runner is fabricated, the conductive runner having a plurality of taps at uniform impedance intervals along the runner, the taps spaced along the runner such that the variation of impedance of the runner between adjacent taps due to presence of a stress migration void in the conductive runner is a detectable portion of the impedance between the adjacent taps absent stress migration voids;

a constant current source coupled to the stress migration test device for driving a known current into the conductive runner;

a plurality of switches capable of providing selected ones of the taps to first and second output nodes; and

a control circuit for controlling the state of the plurality of switches to couple selected ones of the taps to the first and second output nodes.

2. An integrated circuit as recited in claim 1, wherein the first and second output nodes are coupled to dedicated leads of the integrated circuit.

3. An integrated circuit as recited in claim 1, wherein the first and second output nodes are coupled to shared leads of the integrated circuit

4. An integrated circuit as recited in claim 1, wherein the plurality of switches comprises:

a first set of switches coupled between respective taps and a first output node, the first set of switches controlled by a first switching and selection circuit; and

a second set of switches coupled between respective taps and a second output node, the second set of switches controlled by a second switching and selection circuit.

5. An integrated circuit as recited in claim 1, wherein the conductive runner defines a width that is the minimum linewidth for the technology in which the runner is fabricated.

6. An integrated circuit as recited in claim 1, wherein the conductive runner defines a length that is at least 400 micrometers long.

7. An integrated circuit as recited in claim 1, wherein the distance between adjacent ones of the plurality of taps encompasses at least ten crystallographic grains of the material of which the conductive runner is fabricated.

8. An integrated circuit as recited in claim 1, wherein tap conductors extending from the conductive runner to taps are of the same linewidth as the conductive runner.

9. An integrated circuit as recited in claim 1, wherein the conductive runner is comprised of two conductive materials providing parallel conduction paths of different impedances.

10. An integrated circuit as recited in claim 1, wherein the conductive runner extends unidirectionally.

11. An integrated circuit as recited in claim 1, wherein the conductive runner serpentines back and forth boustrophedonically.

12. An integrated circuit as recited in claim 1, wherein the conductive runner is fabricated on at least two levels of interconnects.

13. An integrated circuit as recited in claim 1, further comprising bond pads on the substrate along at least one edge thereof, the bond pads being between an area for circuit layout of the circuits and the at least one edge.

14. An integrated circuit as recited in claim 13, wherein the stress migration test device is fabricated in a layer beneath the layer in which the bond pads are fabricated.

15. An integrated circuit as recited in claim 13, wherein the stress migration test device is fabricated between the bond pads and the at least one edge.

16. An integrated circuit as recited in claim 13, wherein the stress migration test device is fabricated between the bond pads and the area for circuit layout.

17. An integrated circuit as recited in claim 13, wherein the stress migration test device is fabricated within the area for circuit layout.

18. A method for determining the presence or absence of stress migration voids in a conductor of an integrated circuit, comprising the steps of:

fabricating on a substrate a conductive runner having a length sufficient to develop axial stress above the threshold for nucleating voids for the technology in which the runner is fabricated;

providing taps at equal impedance intervals along the runner, the conductive runner between two taps defining a section of the conductive runner;

passing a known current through the conductive runner;

coupling selected ones of the taps to first and second leads of the integrated circuit;

measuring the voltage developed between the selected taps at the first and second leads;

calculating an impedance of the section of the conductive runner between the selected taps;

normalizing the impedance of the section of the conductive runner between the selected taps by a nominal impedance to generate an impedance ratio; and

comparing the impedance ratio to an impedance ratio threshold to determine whether a stress migration void is present in the section of the conductive runner between the selected taps.

19. A method as recited in claim 18, further comprising the steps of:

indexing the selected taps coupled to leads of the integrated circuit to couple a different section of the conductive runner to the first and second leads of the integrated circuit; and

developing an impedance of the different section of the conductive runner.

20. A method as recited in claim 19, further comprising the step of:

repeating the indexing and impedance developing steps until an impedance has been developed for all sections of the conductive runner.

21. A method as recited in claim 20, further comprising the step of:

generating the nominal impedance from the impedances developed for the sections of the conductive runner.

22. A method as recited in claim 21, wherein generating a nominal impedance from the impedances developed for the sections of the conductive runner comprises generating the nominal impedance as an average of the impedances developed for the sections of the conductive runner.

23. A method for determining the presence or absence of stress migration voids in a conductor of an integrated circuit, comprising the steps of:

fabricating on a substrate a conductive runner having a length sufficient to develop axial stress above the threshold for nucleating voids for the technology in which the runner is fabricated;

providing taps at impedance intervals along the runner, the conductive runner between two taps defining a section of the conductive runner;

passing a known current through the conductive runner;

coupling selected ones of the taps to first and second leads of the integrated circuit;

measuring the voltage developed between the selected taps at the first and second leads;

calculating an impedance of the section of the conductive runner between the selected taps;

normalizing the impedance of the section of the conductive runner between the selected taps by an expected impedance for the conductive runner between the selected taps to generate an impedance ratio; and

comparing the impedance ratio to an impedance threshold to determine whether a stress migration void is present in the section of the conductive runner between the selected taps.

24. A method as recited in claim 23, further comprising the steps of:

indexing the taps defining which two taps are coupled to the first and second leads; and

developing an impedance of the section of the conductive runner between the selected taps.

25. A method as recited in claim 24, further comprising the step of:

repeating the indexing and impedance developing steps until an impedance has been developed for all of the sections of the conductive runner.

26. A method as recited in claim 25, further comprising the step of:

generating the nominal impedance from the impedances developed for the sections of the conductive runner.

27. A method as recited in claim 26, wherein generating a nominal impedance from the impedances developed for the sections of the conductive runner comprises generating the nominal impedance as an average of the impedances developed for the sections of the conductive runner.

28. A method as recited in claim 23, further comprising the step of:

based on the comparison, concluding whether there is a stress migration void present in the section of the conductive runner between the selected taps.

29. An integrated circuit, comprising:

a substrate having circuis fabricated thereon, the circuits connected to leads of the integrated circuit;

a stress migration test device fabricated on the substrate, the stress migration test device comprising a conductive runner, the conductive runner having a length sufficient to develop axial stress above the threshold for nucleating voids for the technology in which the runner is fabricated, the conductive runner having a plurality of taps in uniform impedance intervals along the runner, the taps spaced along the runner such that the variation of impedance of the runner between adjacent taps due to presence of a stress migration void in the conductive runner is a detectable portion of the impedance between the adjacent taps absent stress migration voids;

a constant current source coupled to the stress migration test device for driving a known current into the conductive runner;

a plurality of switches capable of providing selected ones of the taps to an output node; and

a control circuit for controlling the state of the plurality of switches to sequentially couple one of the selected taps to the output node.

30. An integrated circuit as recited in claim 29, wherein the distance between adjacent ones of the plurality of taps encompasses at least ten crystallographic grains of the material of which the conductive runner is fabricated.

31. An integrated circuit as recited in claim 29, wherein the conductive runner is comprised of two conductive materials providing parallel conduction paths of different impedances.

32. An integrated circuit as recited in claim 29, wherein the conductive runner is fabricated on at least two levels of interconnects.

33. A method for determining the presence or absence of stress migration voids in a conductor of an integrated circuit, comprising the steps of:

fabricating on a substrate a conductive runner having a length sufficient to develop axial stress above the threshold for nucleating voids for the technology in which the runner is fabricated;

providing taps at equal impedance intervals along the runner, the conductive runner between two taps defining a section of the conductive runner;

passing a known current through the conductive runner;

coupling a selected one of the taps to a lead of the integrated circuit;

measuring the voltage developed between the selected tap at the lead and a reference;

indexing the selected tap coupled to the lead of the integrated circuit to couple an adjacent tap to the lead of the integrated circuit;

measuring the voltage developed between the indexed tap and the reference;

calculating an impedance of the section of the conductive runner between the adjacent taps;

normalizing the impedance of the section of the conductive runner between the adjacent taps by a nominal impedance to generate an impedance ratio; and

comparing the impedance ratio to an impedance ratio threshold to determine whether a stress migration void is present in the sections of the conductive runner between the adjacent taps.

34. A method as recited in claim 33, further comprising the step of:

repeating the indexing and impedance developing steps until an impedance has been developed for all sections of the conductive runner.

35. A method as recited in claim 33, further comprising the step of:

generating the nominal impedance from the impedances developed for the sections of the conductive runner.

36. A method as recited in claim 35, wherein generating a nominal impedance from the impedances developed for the sections of the conductive runner comprises generating the nominal impedance as an average of the impedances developed for the sections of the conductive runner.