High frequency printed circuit board via

• US 20030080835A1
• Filed: 12/03/2002
• Published: 05/01/2003
• Est. Priority Date: 02/25/1999
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A., Hreish, Emad B.
• Granted Patent: US 6,661,316 B2
• Time in Patent Office: Days
• US Class Current: 333/246
• CPC Class Codes: H03H 2001/0085 Multilayer, e.g. LTCC, HTCC, green sheets inside PCB filters H05K
• CPC Class Codes: H03H 7/0115 comprising only inductors and capacitors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence
• CPC Class Codes: H03H 7/075 Ladder networks, e.g. electric wave filters
• CPC Class Codes: H03H 7/1758 Series LC in shunt or branch path H03H7/1791 takes precedence
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0233 Filters, inductors or a magnetic substance
• CPC Class Codes: H05K 1/0251 related to vias or transitions between vias and transmission lines
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/116 Lands, clearance holes or other lay-out details concerning the surrounding of a via
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/09263 Meander
• CPC Class Codes: H05K 2201/09454 Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
• CPC Class Codes: H05K 2201/09672 Superposed layout, i.e. in different planes parallel traces in one plane H05K2201/09236
• CPC Class Codes: H05K 2201/09727 Varying width along a single conductor; Conductors or pads having different widths
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: H05K 3/3421 Leaded components
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Abstract

A printed circuit board (PCB) via, providing a conductor extending vertically between microstrip or stripline conductors formed on separate layers of a PCB, includes a conductive pad surrounding the conductor and embedded within the PCB between those PCB layers. The pad'"'"'s shunt capacitance and the magnitudes of capacitances of other portions of the via are sized relative to the conductor'"'"'s inherent inductance to optimize frequency response characteristics of the via.

Claims

1. An apparatus for conducting a signal between a first conductive strip and a second conductive strip residing at separate first and second elevations on a printed circuit board (PCB), the apparatus comprising:

a conductor extending vertically within the PCB and providing a conductive path for conducting the signal between the first conductive strip and the second conductive strip, the conductor having impedance including inductance; and

capacitive means in contact with the conductor and adding shunt capacitance to the conductive path, wherein the shunt capacitance is sized relative to the conductor'"'"'s impedance to substantially optimize a frequency response characteristic of the conductive path when conducting the signal.

2. The apparatus in accordance with claim 1 wherein the shunt capacitance is sized relative to the conductor'"'"'s impedance such that the conductive path forms a Chebyshev filter.

3. The apparatus in accordance with claim 1 wherein the shunt capacitance is sized relative to the conductor'"'"'s impedance such that the conductive path forms a Butterworth filter.

4. The apparatus in accordance with claim 1 wherein the first shunt capacitance is sized relative to the conductor'"'"'s impedance to substantially maximize a bandwidth characteristic of a frequency response of the conductive path when conducting the signal.

5. The apparatus in accordance with claim 1

wherein the PCB has an upper horizontal surface and a lower horizontal surface;

wherein the first conductive strip resides on the upper horizontal surface;

wherein the second conductive strip resides on the lower horizontal surface;

wherein the conductor extends vertically completely through the PCB; and

wherein said capacitive means comprises;

an upper conductor having a first horizontally planar surface formed on the upper surface conductively linking the conductor to the first conductive strip, and

a lower conductor having a horizontally planar surface formed on the lower surface conductively linking the conductor to the second conductive strip.

6. The apparatus in accordance with claim 5

wherein the upper conductor adds first shunt capacitance to the conductive path,

wherein the lower conductor adds second shunt capacitance to the conductive path, and

wherein the first and second shunt capacitances are sized relative to the conductor'"'"'s impedance to substantially optimize a frequency response characteristic of the conductive path when conducting the signal.

7. The apparatus in accordance with claim 1 wherein the capacitive means comprises a first capacitor embedded within said PCB attached to the conductor at a third elevation between the first and second elevations and adding first shunt capacitance to the signal path.

8. The apparatus in accordance with claim 7 wherein the third elevation resides substantially vertically midway between the first and second elevations.

9. The apparatus in accordance with claim 7

wherein the PCB has a plurality of substrate layers and,

wherein the first capacitor comprises first conductive material formed at the third elevation on one of the substrate layers in contact with the conductor and having a first horizontally planar surface.

10. The apparatus in accordance with claim 9 wherein the first capacitor further comprises second conductive material having a second horizontally planar surface residing proximate to the first planar surface of the first conductive material.

11. The apparatus in accordance with claim 8 wherein the first conductive material surrounds the conductor.

12. The apparatus in accordance with claim 7

wherein the PCB has an upper horizontal surface and a lower horizontal surface;

wherein the first conductive strip resides on the upper horizontal surface;

wherein the second conductive strip resides on the lower horizontal surface;

wherein the conductor extends vertically completely through the PCB; and

wherein said at least one capacitor comprises;

an upper conductor having a horizontally planar surface formed on the upper surface conductively linking the conductor to the first conductive strip, and

a lower conductor having a horizontally planar surface formed on the lower surface conductively linking the conductor to the second conductive strip.

13. The apparatus in accordance with claim 12

wherein the upper conductor having a horizontally planar surface provides second shunt capacitance to the conductive path;

wherein the lower conductor having a horizontally planar surface provides third shunt capacitance to the conductive path; and

wherein the first, second and third shunt capacitances are sized relative to the conductor'"'"'s impedance to substantially optimize a frequency response characteristic of the conductive path when conducting the signal.

14. The apparatus in accordance with claim 13 wherein the first, second and third shunt capacitances are sized relative to the conductor'"'"'s impedance such that the conductive path forms a Chebyshev filter when conducting the signal.

15. The apparatus in accordance with claim 13 wherein the first, second and third shunt capacitances are sized relative to the conductor'"'"'s impedance such that the conductive path forms a Butterworth filter when conducting the signal.

16. The apparatus in accordance with claim 13 wherein the first, second and third shunt capacitances are sized relative to the conductor'"'"'s impedance such that the conductive path has substantially maximal bandwidth when conducting the signal.

17. The apparatus in accordance with claim 7

wherein the PCB has an upper horizontal surface and a lower horizontal surface;

wherein the first elevation resides below the upper horizontal surface;

wherein the second elevation resides above the lower horizontal surface;

wherein the conductor extends vertically completely through the PCB; and

wherein said capacitive means comprises;

an upper conductor having a horizontally planar surface formed on the upper surface conductively linking the conductor to the first conductive strip, and

a lower conductor having a horizontally planar surface formed on the lower surface conductively linking the conductor to the second conductive strip.

18. The apparatus in accordance with claim 17

wherein the upper conductor adds second shunt capacitance to the conductive path;

wherein the lower conductor adds third shunt capacitance to the conductive path; and

wherein the first, second and third shunt capacitances are sized relative to the conductor'"'"'s impedance to substantially optimize a frequency response characteristic of the conductive path when conducting the signal.

19. The apparatus in accordance with claim 18 wherein the first, second and third shunt capacitances are sized relative to the conductor'"'"'s impedance such that the conductive path has substantially maximal bandwidth when conducting the signal.

20. The apparatus in accordance with claim 1 wherein the capacitive means comprises a plurality of capacitors embedded within said PCB and attached to the conductor at elevations between the first and second elevations.

21. An improvement to a printed circuit board (PCB) via including a conductor providing a conductive path for conducting a signal between a first conductive strip and a second conductive strip formed at separate first and second elevations of the PCB, the improvement comprising:

a capacitor embedded within the PCB in contact with the conductor and providing substantial first shunt capacitance at a position along the conductor between the first and second elevations.

22. The improvement to a PCB via in accordance with claim 21 wherein the conductor has impedance, and wherein the first shunt capacitance is sized relative to the conductor'"'"'s impedance to substantially optimize a frequency response characteristic of the conductive path.

23. The improvement to a PCB via in accordance with claim 21 wherein the conductor has impedance, and wherein the first shunt capacitance is sized relative to the conductor'"'"'s impedance to substantially maximize a bandwidth of a frequency response of the conductive path.

24. An apparatus for conducting a signal between a first conductive strip residing on an upper surface of a printed circuit board (PCB) and a second conductive strip residing on a lower surface of a printed circuit board, the apparatus comprising:

a conductor extending vertically within the PCB and providing a signal path for conducting the signal, said conductor having impedance including first series inductance;

first capacitive means formed on the upper surface of the PCB in contact with the conductor and adding first shunt capacitance to the signal path;

second capacitive means formed on the lower surface of the PCB in contact with the conductor and adding second shunt capacitance to the signal path;

a first inductor formed on the upper surface of the PCB linking the first conductive strip to the upper conductor having a horizontally planar surface and adding second series inductance to the signal path;

a second inductor formed on the lower surface of the PCB linking the second conductive strip to the lower conductor having a horizontally planar surface and adding third series inductance to the signal path.

25. The apparatus in accordance with claim 24 wherein the second and third series inductances and the first and second shunt capacitances are sized relative to the conductor'"'"'s impedance to optimize a frequency response characteristic of the signal path.

26. The apparatus in accordance with claim 24 wherein the second and third series inductances and the first and second shunt capacitances are sized relative to the conductor'"'"'s impedance such that the conductive path forms a Butterworth filter.

27. The apparatus in accordance with claim 24 wherein the second and third series inductances and the first and second shunt capacitances are sized relative to the conductor'"'"'s impedance such that the conductive path forms a Chebyshev filter.

28. The apparatus in accordance with claim 24 wherein the second and third series inductances and the first and second shunt capacitances are sized relative to the conductor'"'"'s impedance to substantially maximize a bandwidth of the conductive path.

29. The apparatus in accordance with claim 24 further comprising a third capacitive means embedded within said PCB, attached to the conductor at a third elevation between the first and second elevations, and adding third shunt capacitance to the signal path.

30. The apparatus in accordance with claim 29 wherein the first, second and third shunt capacitances and the second and third series inductances are sized to substantially maximize a bandwidth of the conductive path.