Circuit and signal encoding method for reducing the number of serial ATA external PHY signals

• US 20030081743A1
• Filed: 09/20/2002
• Published: 05/01/2003
• Est. Priority Date: 10/18/2001
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Wang, Tse-Hsien, Chiang, Chin-Yi
• Granted Patent: US 7,020,834 B2
• Time in Patent Office: Days
• US Class Current: 379/93.08
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

The present invention discloses a Circuit for reducing the number of serial ATA external PHY signals, comprising: a serializer/deserializer, connected to a storage medium controller through a set of parallel signal transmitting lines and a set of parallel signal receiving lines, so as to convert signals between parallel and serial specifications; a phase locked loop, connected to the serializer/deserializer so as to generate a clock signal required for data signal transmission; at least one pair of transmitter and receiver, each connected to the serializer/deserializer, each transmitter able to transmit the serial data signal from serializer through a set of serial signal transmitting lines to a serial ATA device, and each receiver able to receive the serial data from the serial ATA device through a set of serial signal receiving lines to the deserializer; and at least one OOB signal detector, each connected to the corresponding receiving lines, so as to detect the out of band signals from the serial ATA device. The present invention also discloses a signal encoding method for reducing the number of serial ATA external PHY signals, wherein an encoder and a decoder are employed to encode control signals and status signals into special data codes transmitted between a serial ATA external PHY and a storage medium controller, so as to minimize the number of interface signals.

Claims

1. A Circuit for reducing the number of serial ATA external PHY signals, comprising:

a serializer/deserializer (SerDes), connected to a storage medium controller through a set of parallel signal transmitting lines and a set of parallel signal receiving lines, so as to convert a parallel signal from said storage medium controller into a serial signal and to convert a serial signal from a serial ATA device into a parallel signal and then to transmit said parallel signal to said storage medium controller;

a phase locked loop, connected to said serializer/deserializer so as to generate clock signals required for data signal transmission and a reference clock signal to said storage medium controller;

at least one transmitter, each connected to said serializer/deserializer, each transmitter able to transmit said serial data signal through a set of serial signal transmitting lines to a serial ATA device;

at least one receiver, each connected to said serializer/deserializer, each receiver able to transmit said serial data signal received from said serial ATA device through a set of serial signal receiving lines to said serializer/deserializer, then said serializer/deserializer converting said serial data signal into parallel data signals, and then transmits said parallel data signals into said storage medium controller; and

at least one OOB (out-of-band) signal detector, each connected to said corresponding receiving lines, so as to detect the out of band signals from said serial ATA device and transmit to said storage medium controller.

2. The Circuit as claimed in claim 1, wherein said serializer/deserializer comprises a serializer and a deserializer.

3. The Circuit as claimed in claim 1, wherein said phase locked loop comprises a transmitting phase locked loop and a receiving phase locked loop.

4. The Circuit as claimed in claim 1, further comprising a power controller, for receiving a plurality of control signals from said storage medium controller so as to control the settings as well as the power state, and for transmitting a PHY ready status signal to said storage medium controller.

5. The Circuit as claimed in claim 4, wherein said power control signals and said PHY ready status signal are multi-level.

6. The Circuit as claimed in claim 4, wherein said PHY ready status signal comprises a transmitting ready signal and a received locked signal from said phase locked loop.

7. The Circuit as claimed in claim 1, further comprising a control signal decoder, connected to said parallel signal transmitting data lines, so as to decode parallel data signals including a transmitted valid signal and to transmit said decoded transmitted valid signal and said parallel data signals to said serializer/deserializer.

8. The Circuit as claimed in claim 1, further comprising a status signal encoder, connected to said serializer/deserializer, so as to encode said parallel data signal and a received quiet signal from said OOB signal detector and then transmit said encoded signals through said parallel signal receiving lines to said storage medium controller.

9. The Circuit as claimed in claim 1, further comprising a transmission path controller, connected to said transmitter and said receiver, so as to control a transmission path for said data signals according to control signal from said storage medium controller.

10. The Circuit as claimed in claim 9, wherein said transmission path controller is a master/slave selector.

11. The Circuit as claimed in claim 10, wherein said master/slave selector comprises a transmitting master/slave selector and a receiving master/slave selector.

12. The Circuit as claimed in claim 1, further comprising a selector, connected to said OOB signal detector, so as to select said received quiet signal from said OOB signal detector to said storage medium controller according to said control signal from said storage medium controller.

13. The Circuit as claimed in claim 8, further comprising a selector, connected to said OOB signal detector, so as to select said received quiet signal from said OOB signal detector to said status signal encoder according to said control signal from said storage medium controller.

14. The Circuit as claimed in claim 1, wherein said phase locked loop further includes a function of switching between transmission rates so as to switch between transmission rates according to a transmission rate selecting signal from said storage medium controller.

15. The Circuit as claimed in claim 1, wherein said phase locked loop further includes a function of switching between a plurality of transmission rates so as to operate said switching function by receiving said control signal from said storage medium controller through a signal line.

16. The Circuit as claimed in claim 1, wherein said Circuit is integrated in a chip.

17. A signal encoding method for reducing the number of serial ATA external PHY signals, wherein an encoder and a decoder are employed to encode control signals and status signals into data signals transmitted between a serial ATA external PHY and a storage medium controller, so as to minimize the number of interface signals.

18. The signal encoding method as claimed in claim 17, wherein said data signals in an interval where a transmitted valid signal is inactive is replaced by all “

1”

digits or all “

0”

digits if said data signals are transmitted from said storage medium controller to said serial ATA external PHY.

19. The signal encoding method as claimed in claim 17, wherein said data signals in an interval where a received quiet signal is active is replaced by all “

1”

digits or all “

0”

digits if said data signals are transmitted from said serial ATA external PHY to said storage medium controller.