PACKAGE FOR MULTIPLE INTEGRATED CIRCUITS AND METHOD OF MAKING

• US 20030082845A1
• Filed: 01/14/2000
• Published: 05/01/2003
• Est. Priority Date: 01/14/2000
• Status: Abandoned Application

• Current Assignee: Amkor Technology Incorporated
• Original Assignee: Amkor Technology Incorporated
• Inventors: HOFFMAN, PAUL, SHIM, IL KWON, DICAPRIO, VINCENT
• Application Number:
  US09/483,212
• Publication Number:
  US 20030082845A1
• Time in Patent Office: Days
• US Class Current: 438/106
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/85424 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85455 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/85464 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/8547 : Zirconium (Zr) as principal constituent
• CPC Class Codes: H01L 2224/92147 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Abstract of Disclosure

Embodiments of integrated circuit packages for housing a plurality of integrated circuits are disclosed, along with methods of making the packages. One embodiment of a package includes a substrate having a first surface with first metallizations thereon and an opposite second surface with second metallizations thereon. One or more apertures extend through the substrate between the first and second surfaces. Conductive vias also extend through the substrate. Eachof the vias electrically connect one or more of the first and second metallizations. A first integrated circuit having a first surface with first bond pads thereon and an opposite second surface is attached to the second surface of the substrate so that the first bond pads are superimposed with an aperture. At least one second integrated circuit is attached to the second surface of the first integrated circuit. An opposite surface of the second integrated circuit has edge bond pads thereon. Each of a plurality of first bond wires are electrically connected between a first metallization and a first bond pad. Each of a plurality of second bond wires are electrically connected between a second metallization and a second bond pad. Accordingly, the second integrated circuit is electrically connected to first metallizations by way of the viasthrough the substrate. The integrated circuits may be electrically connected to each other. In a second package embodiment, the first integrated circuit is a flip chip integrated circuit. In the second embodiment, apertures through the substrate are not necessary.

Claims

1. An integrated circuit package comprising:

a substrate having a first surface having first metallizations thereon, an opposite second surface having second metallizations thereon, one or more apertures between the first and second surfaces, and conductive vias through the substrate between the first and second surfaces, each of said vias electrically connecting one or more of said first and second metallizations;

a first integrated circuit having a first surface with first bond pads thereon, and an opposite second surface, wherein the first bond pads are superimposed with an aperture;

at least one second integrated circuit having a first surface and an opposite second surface with conductive second bond pads thereon, wherein the first surface of the at least one second integrated circuit is on the second surface of the first integrated circuit;

a plurality of first bond wires, each first bond wire being electrically connected between a first metallization and a first bond pad, said first bond wires extending through an aperture; and

" a plurality of second bond wires, each second bond wire being electrically connected between a second metallization and a second bond pad, whereby the second integrated circuit is 20 electrically connected to first metallizations.

2. The package of claim 1, wherein at least one first bond pad is electrically connected to at least one second bond pad.

3. The package of claim 1, wherein the first and second integrated circuits are the same type of integrated circuit.

4. The package of claim 1, wherein the first and second integrated circuits are different types of integrated circuits.

5. The package of claim 1, wherein at least some of the first bond pads are center bond pads, and the second bond pads are edge bond pads.

6. The package of claim 1, further comprising a plurality of said second integrated circuits.

7. The package of claim 6, wherein at least one second bond pad of one second integrated circuit is electrically connected to at least one second bond pad of another second 10 integrated circuit.

8. The package of claim 1, wherein said substrate includes a plurality of said apertures, each of said apertures superimposes first bond pads, and bond wires extend through each aperture and electrically connect first bond pads to first metallizations.

9. The package of claim 8, wherein at least some of the first bond pads are edge bond pads.

10. The package of claim 9, wherein the first and second bond pads are edge bond 20 pads.

11. The package of claim 8, further comprising a plurality of solder balls each on a first metallization of the first surface of the substrate, wherein each solder ball is electrically connected to at least one first or second bond pad, and solder balls are located adjacent to opposite sides of each said aperture.

12. The package of claim 11, wherein at least some of the first bond pads are edge bond pads.

13. The package of claim 8, wherein at least one first bond pad is electrically connected to at least one second bond pad.

14. An integrated circuit package comprising:

a substrate having a first surface having first metallizations thereon, an opposite second 35 surface having second metallizations thereon, and a plurality of conductive vias through the substrate between the first and second surfaces, each of said vias electrically connecting one or more of said first and second metallizations;

a flip chip integrated circuit having a first surface with first bond pads thereon and an opposite second surface, wherein the first bond pads face the second surface of the substrate, and each said bond pad is electrically connected to at least one of said second metallizations;

at least one second integrated circuit having a first surface and an opposite second surface with second bond pads thereon, wherein the first surface of the at least one second integrated

circuit is on the second surface of the first integrated circuit; and

a plurality of bond wires, each bond wire being electrically connected between a second bond pad and a second metallization, whereby the at least one second integrated circuit is electrically connected to first metallizations.

15. The package of claim 14, wherein the second bond pads are edge bond pads.

16. The package of claim 15, further comprising a plurality of said second integrated 20 circuits.

17. A method of making a package containing a plurality of integrated circuits, the method comprising:

providing a substrate having a first surface having first metallizations thereon, an opposite second surface having second metallizations thereon, one or more apertures between the first and second surfaces, and conductive vias through the substrate between the first and second surfaces, each of said vias electrically connecting one or more of said first and second metallizations;

providing a first integrated circuit having a first surface with first bond pads thereon and an opposite second surface, and mounting the first surface of said first integrated circuit on the second surface of the substrate so that the first bond pads are superimposed with an aperture providing at least one second integrated circuit having a first surface and an opposite second surface with second bond pads thereon, and mounting the first surface of said at least one second integrated circuit on the second surface of the first integrated circuit;

providing a plurality of first bond wires, and electrically connecting each first bond wire between a first bond pad and a first metallization through an aperture; and

providing a plurality of second bond wires, and electrically connecting each second bond wires between a second bond pad and a second metallization, whereby the second integrated circuit is electrically connected to first metallizations.

18. The method of claim 17, further comprising electrically connecting at least one of said first bond pads to at least one of said second bond pads.

19. The method of claim 18, wherein at least some of the first bond pads are center 15 bond pads, and the second bond pads are edge bond pads.

20. The method of claim 19, wherein the first and second bond pads are edge bond pads.

21. The method of claim 17, further comprising providing a plurality of said apertures, and mounting said first integrated circuit device so that each of said apertures superimposes first bond pads.

22. The method of claim 21, wherein at least some of the first bond pads are center 25 bond pads, and the second bond pads are edge bond pads.

23. The method of claim 22, wherein the first and second bond pads are edge bond pads.

26. The method of claim 23, wherein at least some of the first bond pads are center bond pads, and the second bond pads are edge bond pads.

24. A method of making a plurality of packages each containing a plurality of integrated circuits, the method comprising:

providing a planar substrate having a plurality of package sites thereon, wherein each package site has a first surface having first metallizations thereon, an opposite second surface having second metallizations thereon, one or more apertures between the first and second surfaces, and a one or more conductive vias through the substrate between the first and second surfaces, each of said vias electrically connecting one or more of said first and second metallizations;

providing a plurality of first integrated circuits each having a first surface with conductive first bond pads thereon, and an opposite second surface, and placing the first surface of said first integrated circuit on the second surface of the substrate at each package site so that the first bond pads are superimposed with an aperture of the package site;

providing a plurality of second integrated circuits each having a first surface and an opposite second surface with conductive second bond pads thereon, and placing the first surface of at least one second integrated circuit on the second surface of the first integrated circuit of each package site;

providing a plurality of conductive first bond wires for each package site, and electrically

connecting each first bond wire between a first bond pad and a first metallization through an aperture at the respective package sites; and

providing a plurality of conductive second bond wires for each package site, and electrically connecting each second bond wire between a second bond pad and a second metallization at the respective package sites, whereby the second integrated circuits are electrically connected to first metallizations of the respective package site.

25. The method of claim 24, further comprising electrically connecting at least one of said first bond pads to at least one of said second bond pads.

27. The method of claim 24, further comprising providing a plurality of said apertures at each package site, and mounting the first integrated circuit at each package site so that each of said apertures superimposes first bond pads.

28. The method of claim 27, further comprising electrically connecting at least one of said first bond pads to at least one of said second bond pads.

29. The method of claim 27, wherein at least some of the first bond pads are center bond pads, and the second bond pads are edge bond pads.

30. The method of claim 27, wherein the first bond pads are edge bond pads.

31. A method of making a package containing a plurality of integrated circuits, the method comprising:

providing a substrate having a first surface having first metallizations thereon, an opposite second surface having second metallizations thereon, and a plurality of conductive vias through the substrate between the first and second surfaces, each of said vias electrically connecting one or more of said first and second metallizations;

providing a flip chip integrated circuit having a first surface with first bond pads thereon and an opposite second surface;

mounting the first surface of the flip chip integrated circuit on the second surface of the substrate so that the first bond pads face the second surface of the substrate, and electrically connecting said at least some of said first bond pads to respective said second metallizations;

providing at least one second integrated circuit having a first surface and an opposite second surface with conductive second bond pads thereon, and mounting the first surface of the at least one second integrated circuit on the second surface of the first integrated circuit; and

providing a plurality of bond wires, and electrically connecting each bond wire between a second bond pad and a second metallization, whereby the at least one second integrated circuit is electrically connected to first metallizations.

32. The method of claim 31, wherein the second bond pads are edge bond pads.