Method of incorporating deep trench into shallow trench isolation process without added masks

• US 20030082888A1
• Filed: 05/20/2002
• Published: 05/01/2003
• Est. Priority Date: 10/31/2001
• Status: Abandoned Application

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Ching-Fu
• Application Number:
  US10/150,074
• Publication Number:
  US 20030082888A1
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

The present invention provides a method of forming a deep trench device and a shallow trench isolation comprising providing a semiconductor substrate having a first opening thereon. A dielectric layer is deposited on the semiconductor substrate and into the first opening. A mask layer is formed on the first dielectric layer. The mask layer is transferred a pattern consisting of database of reverse shallow trench isolation and database of the deep trench. The partial first dielectric layer and semiconductor substrate are removed to form a second opening below the first opening. The deep trench device is formed in the second opening and the shallow trench isolation in the first opening.

Claims

1. A method of forming a deep trench device and a shallow trench isolation, said method comprising:

providing a semiconductor substrate having a first opening thereon;

depositing a first dielectric layer on said semiconductor substrate and into said first opening;

forming a mask layer on said first dielectric layer, said mask layer transferred a pattern consisting of database of reverse shallow trench isolation and database of said deep trench device;

removing partial said first dielectric layer and partial said semiconductor substrate to form a second opening below said first opening;

forming said deep trench device in said second opening; and

forming said shallow trench isolation in said first opening.

2. The method according to claim 1, wherein said providing step comprises a silicon nitride layer on partial said semiconductor substrate without said first opening.

3. The method according to claim 2, wherein said step of removing partial said first dielectric layer and partial said semiconductor substrate further comprises removing partial said silicon nitride layer.

4. The method according to claim 1, wherein said forming said deep trench device comprises:

forming a liner oxide layer at a sidewall of said second opening;

depositing a conductive layer in said second opening and on said semiconductor substrate; and

etching back said conductive layer to form said deep trench device.

5. The method according to claim 4, wherein said conductive layer comprises a polysilicon layer.

6. The method according to claim 1, wherein said forming said shallow trench isolation comprises:

depositing a second dielectric layer over said semiconductor substrate; and

planarizing said second dielectric layer by chemical mechanical polishing.

7. The method according to claim 1, wherein said step of removing partial said first dielectric layer and partial said semiconductor substrate is to remove said first dielectric layer that is beside said first opening and on said second opening.

8. The method according to claim 1, wherein said first opening has a size larger than said second opening.

9. A method of forming a deep trench device and a plurality of shallow trench isolation devices, said method comprising:

providing a semiconductor substrate having a plurality of first openings thereon;

depositing a dielectric layer on said semiconductor substrate and into said first openings;

forming a mask layer on said dielectric layer, said mask layer transferred a pattern consisting of database of reverse shallow trench isolation and database of said deep trench device;

removing partial said dielectric layer that is beside said first openings and partial in one of said first openings, and removing partial said semiconductor substrate in said one of said first openings to form a second opening below said one of said first openings;

forming said deep trench device in said second opening; and

forming said shallow trench isolation devices in said first openings.

10. The method according to claim 9, wherein said providing step comprises a silicon nitride layer on partial said semiconductor substrate without said first openings.

11. The method according to claim 9, wherein said dielectric layer comprises an oxide layer.

12. The method according to claim 9, wherein said forming said deep trench device comprises:

forming a liner oxide layer at a sidewall of said second opening;

depositing a polysilicon layer in said second opening and on said semiconductor substrate; and

etching back said polysilicon layer to form said deep trench device.

13. The method according to claim 9, wherein said forming said shallow trench isolation devices comprises:

depositing an oxide layer over said semiconductor substrate; and

planarizing said oxide layer by chemical mechanical polishing.