Electronic control device having control and monitoring CPUS

• US 20030083802A1
• Filed: 10/02/2002
• Published: 05/01/2003
• Est. Priority Date: 10/31/2001
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Miyano, Hidemasa
• Granted Patent: US 6,820,000 B2
• Time in Patent Office: Days
• US Class Current: 701/114
• CPC Class Codes: G05B 23/0286 Modifications to the monitored process, e.g. stopping operation or adapting control
• CPC Class Codes: G05B 9/02 electric

Abstract

The engine ECU includes a control CPU and a monitoring CPU. The control CPU 11 has a vehicular engine control function and an electronic throttle control function. The monitoring CPU is connected to the control CPU in an intercommunicative manner. The monitoring CPU communicates with the control CPU to receive data at least on the throttle control from the control CPU. The monitoring CPU determines whether the data from the control CPU is properly received. If the date is not properly received, the monitoring CPU resets the control CPU.

Claims

1. A control CPU monitoring method for an electronic control device having a control CPU and a monitoring CPU that is connected with the control CPU in an intercommunicative manner, the method comprising steps of:

transmitting control operation data from the control CPU to the monitoring CPU in a predetermined cycle;

determining a data receiving condition of the monitoring CPU; and

resetting the control CPU by the monitoring CPU when the data receiving condition is determined faulty.

2. The control CPU monitoring method as in claim 1, wherein the determining step determines that data receiving condition is faulty when a length of period for which the monitoring CPU fails to receive the data is longer than a predetermined length.

3. The control CPU monitoring method as in claim 1 or 2, wherein:

the transmitting step transmits monitoring data that is updated every data transmission, in addition to the control operation data, from the control CPU to the monitoring CPU; and

the determining step determines the data receiving condition based on whether the monitoring data is updated.

4. The control CPU monitoring method as in claim 3, wherein the monitoring data includes a number of times that the data is updated upon the data transmission.

5. The control CPU monitoring method as in claim 3 or 4, further comprising a step of:

transmitting response data in response to the monitoring data from the monitoring CPU to the control CPU in synchronization with the data transmission from the control CPU to the monitoring CPU.

6. The control CPU monitoring method as in any one of claims 1 through 5, further comprising steps of:

inputting a watchdog pulse with a predetermined cycle from the control CPU to a monitoring circuit; and

outputting a first reset signal from the monitoring circuit to a reset terminal of the control CPU when periodicity of the watchdog pulse is disrupted,

wherein the resetting step resets the control CPU by a second reset signal outputted from the monitoring CPU and inputted to the control CPU via the reset terminal.

7. The control CPU monitoring method as in any one of claims 1 through 6, wherein the control operation data includes data on a vehicle operation control.

8. The control CPU monitoring method as in claim 7, wherein the vehicle operation control data includes data on an electronic throttle control.

9. The control CPU monitoring method as in claim 7, wherein the vehicle operation control data further includes data on an engine control.

10. The control CPU monitoring method as in claims 5, further comprising steps of:

determining whether the control CPU has successfully received the response data; and

outputting a third reset signal from the control CPU to the monitoring CPU when it is determined that the control CPU has failed to receive the response data.

12. The electronic control device as in claim 7, further comprising a monitoring circuit for monitoring operations of the control CPU,

wherein the monitoring circuit receives a watchdog pulse that is outputted from the control CPU and inverted in a predetermined cycle, and outputs a third reset signal to the control CPU when periodicity of the cycle is disrupted.

13. The electronic control device as in claim 8, wherein:

the control CPU has a reset terminal for receiving the reset signal from the monitoring circuit; and

the reset signal outputted from the monitoring CPU is also applied to the reset terminal.

14. The electronic control device as in any one of claims 7 through 9, wherein the control CPU has an engine control function and an electronic throttle control function for a vehicle.

15. The electronic control device as in claim 10, wherein the monitoring CPU receives data at least on the electronic throttle control for monitoring electronic throttle control operations.

11. An electronic control device comprising:

a control CPU; and

a monitoring CPU for monitoring control operations of the control CPU,

wherein the monitoring CPU is connected with the control CPU in an intercommunicative manner to receive data on the control operations of the control CPU;

wherein a first reset signal is outputted from the monitoring CPU to the control CPU, and

wherein a second reset signal is outputted from the control CPU to the monitoring CPU.