Method, apparatus, and computer program for evaluating noise immunity of a semiconductor device

• US 20030083857A1
• Filed: 10/23/2002
• Published: 05/01/2003
• Est. Priority Date: 10/25/2001
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Benno, Hiroshi, Takahashi, Eiji, Saito, Yoshiyuki, Fukumoto, Yukihiro
• Granted Patent: US 7,233,889 B2
• Time in Patent Office: Days
• US Class Current: 703/18
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method of evaluating noise immunity of a semiconductor device is provided. An actual circuit including the semiconductor device is represented by an equivalent circuit which has a target equivalent circuit, a noise source equivalent circuit, and an external equivalent circuit connected in parallel. The target equivalent circuit represents the semiconductor device. The noise source equivalent circuit represents a noise source outside the semiconductor device, and supplies noise to the target equivalent circuit. The external equivalent circuit represents a circuit outside the semiconductor device. The noise immunity is evaluated based on a voltage or current which arises in the target equivalent circuit by the noise. In this way, the immunity of the semiconductor device against extraneous noise can be evaluated in consideration of the effects of the circuitry outside the semiconductor device.

Claims

1. A method of evaluating noise immunity of a semiconductor device, using an equivalent circuit that represents an actual circuit which includes the semiconductor device and a noise source outside the semiconductor device,

the equivalent circuit including a target circuit and a noise circuit which are connected with each other, the target circuit representing the semiconductor device whereas the noise circuit representing the noise source and supplying noise to the target circuit,

the target circuit including a logic circuit and at least one of a power circuit and a ground circuit which are connected in series with each other, the logic circuit representing a logic part of the semiconductor device, the power circuit representing a power supplying part of the semiconductor device including power pins and wiring, the ground circuit representing a grounding part of the semiconductor device including ground pins and wiring,

the method comprising the steps of:

calculating at least one of (a) a voltage arising in the logic circuit due to the noise and (b) a current flowing through the target circuit due to the noise, using an impedance of each circuit in the target circuit; and

evaluating the noise immunity of the semiconductor device according to the calculation result.

2. The method of claim 1,

wherein the equivalent circuit further includes an external circuit representing a circuit which is included in the actual circuit and is located outside the semiconductor device, the external circuit, the target circuit, and the noise circuit being connected in parallel with each other, and

the calculating step performs the calculation, further using an impedance of the external circuit.

3. The method of claim 1,

wherein the logic part of the semiconductor device includes a plurality of circuit blocks,

the logic circuit in the equivalent circuit includes a plurality of block circuits which are in a one-to-one correspondence with the plurality of circuit blocks and are connected in parallel with each other,

each block circuit includes a block logic circuit and at least one of a block power circuit and a block ground circuit which are connected in series with each other, the block logic circuit representing a logic part of a corresponding circuit block, the block power circuit representing a power supplying part of the corresponding circuit block including power wiring, and the block ground circuit representing a grounding part of the corresponding circuit block including ground wiring, and

the calculating step calculates at least one of:

(1) a voltage arising in the block logic circuit in each block circuit due to the noise;

(2) a voltage arising in the block power circuit in each block circuit due to the noise;

(3) a voltage arising in the block ground circuit in each block circuit due to the noise; and

(4) a current flowing through each block circuit due to the noise, using an impedance of the power circuit, an impedance of the ground circuit, and an impedance of each circuit included in the plurality of block circuits.

4. The method of claim 3,

wherein the equivalent circuit further includes an external circuit representing a circuit which is included in the actual circuit and is located outside the semiconductor device, the external circuit, the target circuit, and the noise circuit being connected in parallel with each other, and

the calculating step performs the calculation, further using an impedance of the external circuit.

5. A method of evaluating noise immunity of a semiconductor device, using an equivalent circuit that represents an actual circuit which includes the semiconductor device and a plurality of noise sources outside the semiconductor device, the semiconductor device including a plurality of circuit blocks which are each influenced by a different one of the plurality of noise sources,

the equivalent circuit including a plurality of partial circuits which are in a one-to-one correspondence with the plurality of circuit blocks, the plurality of partial circuits being connected to the same ground,

each partial circuit including a block circuit and a noise circuit which are connected with each other, the block circuit representing a corresponding circuit block, whereas the noise circuit representing a noise source which influences the corresponding circuit block and supplying noise to the block circuit,

the block circuit including a block logic circuit and at least one of a block power circuit and a block ground circuit which are connected in series with each other, the block logic circuit representing a logic part of the corresponding circuit block, the block power circuit representing a power supplying part of the corresponding circuit block including power wiring, and the block ground circuit representing a grounding part of the corresponding circuit block including ground wiring,

the method comprising the steps of:

calculating at least one of;

(1) a voltage arising in the block logic circuit of the block circuit in each partial circuit due to the noise;

(2) a voltage arising in the block power circuit of the block circuit in each partial circuit due to the noise;

(3) a voltage arising in the block ground circuit of the block circuit in each partial circuit due to the noise; and

(4) a current flowing through the block circuit in each partial circuit due to the noise, using an impedance of each circuit of the block circuit in each partial circuit; and

evaluating the noise immunity of the semiconductor device according to the calculation result.

6. The method of claim 5,

wherein each partial circuit in the equivalent circuit further includes an external circuit representing a circuit which is included in the actual circuit and is located outside the semiconductor device, the external circuit, the block circuit, and the noise circuit being connected in parallel with each other, and

the calculating step performs the calculation, further using an impedance of the external circuit in each partial circuit.

7. An apparatus of evaluating noise immunity of a semiconductor device, using an equivalent circuit that represents an actual circuit which includes the semiconductor device and a noise source outside the semiconductor device,

the equivalent circuit including a target circuit and a noise circuit which are connected with each other, the target circuit representing the semiconductor device, whereas the noise circuit representing the noise source and supplying noise to the target circuit,

the target circuit including a logic circuit and at least one of a power circuit and a ground circuit which are connected in series with each other, the logic circuit representing a logic part of the semiconductor device, the power circuit representing a power supplying part of the semiconductor device including power pins and wiring, the ground circuit representing a grounding part of the semiconductor device including ground pins and wiring,

the apparatus comprising:

storing means for storing an impedance of each circuit included in the target circuit;

calculating means for calculating at least one of (a) a voltage arising in the logic circuit due to the noise and (b) a current flowing through the target circuit due to the noise, using the impedance of each circuit stored in the storing means; and

evaluating means for evaluating the noise immunity of the semiconductor device according to the calculation result.

8. The apparatus of claim 7,

wherein the equivalent circuit further includes an external circuit representing a circuit which is included in the actual circuit and is located outside the semiconductor device, the external circuit, the target circuit, and the noise circuit being connected in parallel with each other,

the storing means further stores an impedance of the external circuit, and

the calculating means performs the calculation, further using the impedance of the external circuit stored in the storing means.

9. The apparatus of claim 7,

wherein the logic part of the semiconductor device includes a plurality of circuit blocks,

the logic circuit in the equivalent circuit includes a plurality of block circuits which are in a one-to-one correspondence with the plurality of circuit blocks and are connected in parallel with each other,

each block circuit includes a block logic circuit and at least one of a block power circuit and a block ground circuit which are connected in series with each other, the block logic circuit representing a logic part of a corresponding circuit block, the block power circuit representing a power supplying part of the corresponding circuit block including power wiring, and the block ground circuit representing a grounding part of the corresponding circuit block including ground wiring,

the storing means stores an impedance of the power circuit, an impedance of the ground circuit, and an impedance of each circuit included in the plurality of block circuits, and

the calculating means calculates at least one of:

(1) a voltage arising in the block logic circuit in each block circuit due to the noise;

(2) a voltage arising in the block power circuit in each block circuit due to the noise;

(3) a voltage arising in the block ground circuit in each block circuit due to the noise; and

(4) a current flowing through each block circuit due to the noise, using the impedances stored in the storing means.

10. The apparatus of claim 9,

wherein the equivalent circuit further includes an external circuit representing a circuit which is included in the actual circuit and is located outside the semiconductor device, the external circuit, the target circuit, and the noise circuit being connected in parallel with each other,

the storing means further stores an impedance of the external circuit, and

the calculating means performs the calculation, further using the impedance of the external circuit stored in the storing means.

11. An apparatus of evaluating noise immunity of a semiconductor device, using an equivalent circuit that represents an actual circuit which includes the semiconductor device and a plurality of noise sources outside the semiconductor device, the semiconductor device including a plurality of circuit blocks which are each influenced by a different one of the plurality of noise sources,

the equivalent circuit including a plurality of partial circuits which are in a one-to-one correspondence with the plurality of circuit blocks, the plurality of partial circuits being connected to the same ground,

each partial circuit including a block circuit and a noise circuit which are connected with each other, the block circuit representing a corresponding circuit block, whereas the noise circuit representing a noise source which influences the corresponding circuit block and supplying noise to the block circuit,

the block circuit including a block logic circuit and at least one of a block power circuit and a block ground circuit which are connected in series with each other, the block logic circuit representing a logic part of the corresponding circuit block, the block power circuit representing a power supplying part of the corresponding circuit block including power wiring, and the block ground circuit representing a grounding part of the corresponding circuit block including ground wiring,

the apparatus comprising:

storing means for storing an impedance of each circuit of the block circuit in each partial circuit;

calculating means for calculating at least one of;

(1) a voltage arising in the block logic circuit of the block circuit in each partial circuit due to the noise;

(2) a voltage arising in the block power circuit of the block circuit in each partial circuit due to the noise;

(3) a voltage arising in the block ground circuit of the block circuit in each partial circuit due to the noise; and

(4) a current flowing through the block circuit in each partial circuit due to the noise, using the impedance of each circuit stored in the storing means; and

evaluating means for evaluating the noise immunity of the semiconductor device according to the calculation result.

12. The apparatus of claim 11,

wherein each partial circuit in the equivalent circuit further includes an external circuit representing a circuit which is included in the actual circuit and is located outside the semiconductor device, the external circuit, the block circuit, and the noise circuit being connected in parallel with each other,

the storing means further stores an impedance of the external circuit in each partial circuit, and

the calculating means performs the calculation, further using the impedance of the external circuit stored in the storing means.

13. A computer program which is executed by a computer to realize an apparatus of evaluating noise immunity of a semiconductor device using an equivalent circuit that represents an actual circuit which includes the semiconductor device and a noise source outside the semiconductor device,

the equivalent circuit including a target circuit and a noise circuit which are connected with each other, the target circuit representing the semiconductor device, whereas the noise circuit representing the noise source and supplying noise to the target circuit,

the target circuit including a logic circuit and at least one of a power circuit and a ground circuit which are connected in series with each other, the logic circuit representing a logic part of the semiconductor device, the power circuit representing a power supplying part of the semiconductor device including power pins and wiring, the ground circuit representing a grounding part of the semiconductor device including ground pins and wiring,

the computer program comprising the steps of:

calculating at least one of (a) a voltage arising in the logic circuit due to the noise and (b) a current flowing through the target circuit due to the noise, using an impedance of each circuit in the target circuit; and

evaluating the noise immunity of the semiconductor device according to the calculation result.

14. The computer program of claim 13,

wherein the equivalent circuit further includes an external circuit representing a circuit which is included in the actual circuit and is located outside the semiconductor device, the external circuit, the target circuit, and the noise circuit being connected in parallel with each other, and

the calculating step performs the calculation, further using an impedance of the external circuit.

15. The computer program of claim 13,

wherein the logic part of the semiconductor device includes a plurality of circuit blocks,

the logic circuit in the equivalent circuit includes a plurality of block circuits which are in a one-to-one correspondence with the plurality of circuit blocks and are connected in parallel with each other,

each block circuit includes a block logic circuit and at least one of a block power circuit and a block ground circuit which are connected in series with each other, the block logic circuit representing a logic part of a corresponding circuit block, the block power circuit representing a power supplying part of the corresponding circuit block including power wiring, and the block ground circuit representing a grounding part of the corresponding circuit block including ground wiring, and

the calculating step calculates at least one of:

(1) a voltage arising in the block logic circuit in each block circuit due to the noise;

(2) a voltage arising in the block power circuit in each block circuit due to the noise;

(3) a voltage arising in the block ground circuit in each block circuit due to the noise; and

(4) a current flowing through each block circuit due to the noise, using an impedance of the power circuit, an impedance of the ground circuit, and an impedance of each circuit included in the plurality of block circuits.

16. The computer program of claim 15,

wherein the equivalent circuit further includes an external circuit representing a circuit which is included in the actual circuit and is located outside the semiconductor device, the external circuit, the target circuit, and the noise circuit being connected in parallel with each other, and

the calculating step performs the calculation, further using an impedance of the external circuit.

17. A computer program which is executed by a computer to realize an apparatus of evaluating noise immunity of a semiconductor device using an equivalent circuit that represents an actual circuit which includes the semiconductor device and a plurality of noise sources outside the semiconductor device, the semiconductor device including a plurality of circuit blocks which are each influenced by a different one of the plurality of noise sources,

the equivalent circuit including a plurality of partial circuits which are in a one-to-one correspondence with the plurality of circuit blocks, the plurality of partial circuits being connected to the same ground,

each partial circuit including a block circuit and a noise circuit which are connected with each other, the block circuit representing a corresponding circuit block, whereas the noise circuit representing a noise source which influences the corresponding circuit block and supplying noise to the block circuit,

the block circuit including a block logic circuit and at least one of a block power circuit and a block ground circuit which are connected in series with each other, the block logic circuit representing a logic part of the corresponding circuit block, the block power circuit representing a power supplying part of the corresponding circuit block including power wiring, and the block ground circuit representing a grounding part of the corresponding circuit block including ground wiring,

the computer program comprising the steps of:

calculating at least one of;

(1) a voltage arising in the block logic circuit of the block circuit in each partial circuit due to the noise;

(2) a voltage arising in the block power circuit of the block circuit in each partial circuit due to the noise;

(3) a voltage arising in the block ground circuit of the block circuit in each partial circuit due to the noise; and

(4) a current flowing through the block circuit in each partial circuit due to the noise, using an impedance of each circuit of the block circuit in each partial circuit; and

evaluating the noise immunity of the semiconductor device according to the calculation result.

18. The computer program of claim 17,

wherein each partial circuit in the equivalent circuit further includes an external circuit representing a circuit which is included in the actual circuit and is located outside the semiconductor device, the external circuit, the block circuit, and the noise circuit being connected in parallel with each other, and

the calculating step performs the calculation, further using an impedance of the external circuit in each partial circuit.

19. A computer-readable storage medium storing a computer program of any of claims 13 to 18.

20. A method of evaluating noise immunity of a semiconductor device, using an equivalent circuit that represents an actual circuit which includes the semiconductor device and a noise source outside the semiconductor device,

the equivalent circuit including a target circuit and a noise circuit which are connected with each other, the target circuit representing the semiconductor device, the noise circuit representing the noise source and supplying noise to the target circuit,

the method comprising the steps of:

calculating an effect resulting in the target circuit from the noise supplied from the noise circuit outside the target circuit; and

evaluating the noise immunity of the semiconductor device according to the calculation result.

21. The method of claim 20,

wherein the equivalent circuit further includes an external circuit connected to the target circuit, the external circuit representing a circuit which is included in the actual circuit and is located outside the semiconductor device, and

the calculating step performs the calculation based upon components of the external circuit.