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Incremental automata verification

  • US 20030083858A1
  • Filed: 10/29/2001
  • Published: 05/01/2003
  • Est. Priority Date: 10/29/2001
  • Status: Active Grant
First Claim
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1. A method of formal verification of a system design, wherein the system is defined by a set of automata, each having a set of states, the method comprising:

  • performing a first verification of a system, beginning with an initial state and finding successor states;

    finding an under-defined state of the system;

    saving execution traces leading up to the under-defined state;

    further defining the under-defined state, thereby generating a newly specified state; and

    performing a second verification of the system beginning with the newly specified state, using the saved execution traces, and finding successor states.

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