Reduced pin-count system interface for gigabit ethernet physical layer devices

• US 20030084195A1
• Filed: 08/24/2001
• Published: 05/01/2003
• Est. Priority Date: 08/24/2001
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Dove, Daniel J.
• Granted Patent: US 7,466,668 B2
• Time in Patent Office: Days
• US Class Current: 709/252
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]

Abstract

A Gigabit Media Independent Interface (RGMII), which is adapted to also implement a ten bit interface (RTBI) that is intended to be an alternative to both the IEEE 802.3z GMII and the TBI is disclosed. The interface has a reduced number of input and output pins, i.e., pin-count, that can implement the above BMII and TBI standards. More particularly, the interface reduces the number of pins required to interconnect the MAC and the PHY from a maximum of 28 pins (TBI) to 12 pins in a cost effective and technology independent manner. The RGMII maps pins to transfer data at the same data rate with control functionality with a minimum number of input and output pins, and does so by utilizing both the rising and falling edges of the clock signal and complies with existing interface specifications set forth in the IEEE standards.

Claims

1. Apparatus for interfacing a media access controller (MAC) and a physical layer device (PHY) in a manner whereby the standards of IEEE 802 are complied with for at least one of the gigabit media independent interface and the ten bit interface, transferring data at a predetermined rate while substantially reducing the required number of input and output pins, said apparatus comprising:

means for multiplexing the data and control signals that are normally applied to a predetermined number of pins to a significantly lesser number of pins and for selectively mapping the data and control signals to the lesser number of pins.

2. Apparatus as defined in claim 1 wherein said multiplexing means multiplexes different significant bits of data on the same set of pins using both edges of a clock signal having the predetermined rate, thereby transferring data at the predetermined rate on the lesser number of pins.

3. Apparatus as defined in claim 1 wherein the clock rate is within the range of about 2.5 MHz and about 125 MHz, with the clock rate being within the range of about 2.5 and about 25 MHz for the ten bit interface and about 125 MHz for the gigabit media independent interface operation.

4. Apparatus as defined in claim 1 wherein said multiplexing means includes means for controlling the relative timing between the clock signal and the data during transmitting and during receiving, the clock and data signals being generated substantially simultaneously when either the MAC or the PHY transmits the signals, such that the data to clock output skew at the transmitter is within +/−

500 picoseconds and the data to clock input skew at the receiver is between about 1 and about 2.8 nanoseconds for clock signal speeds within the range of 2.5 MHz and 125 MHz.

5. Apparatus as defined in claim 3 wherein the clock signal has a duty cycle for gigabit media independent interface operation that is within the range of 45 and 55 percent and a duty cycle for the ten bit interface operation that is within the range of 40 and 60 percent.

6. Apparatus as defined in claim 1 comprising six input pins for use in either the gigabit media independent interface operation or the ten bit interface operation in which:

a transmit reference clock signal TXC is applied to a first pin in the gigabit media independent interface operation and the ten bit interface operation;

8 bits of data are applied to the second through fifth pins on both edges of a clock cycle during the gigabit media independent interface operation and the ten bit interface operation;

2 bits of data are applied to the sixth pin in the ten bit interface operation; and

,

control signals are applied to the second through fifth pin in the gigabit media independent interface operation.

7. Apparatus as defined in claim 1 comprising six output pins for use in either the gigabit media independent interface operation or the ten bit interface operation in which:

a receive reference clock signal RXC is derived from the received data stream and appears on a first pin in the gigabit media independent interface operation and the ten bit interface operation;

8 bits of data are applied to the second through fifth pins on both edges of a clock cycle during the gigabit media independent interface operation and the ten bit interface operation;

2 bits of data are applied to the sixth pin in the ten bit interface operation; and

,

control signals are applied to the second through fifth pin in the gigabit media independent interface operation.

8. A media interface for a media access controller (MAC) and a physical layer device (PHY) that complies with the standards of IEEE 802 for at least gigabit media independent interface operation and the ten bit interface operation, which interface transfers data at a predetermined clock rate on a reduced number of pins, said interface multiplexing the data and control signals that are applied to the reduced number of pins using both edges of said clock signal and for selectively mapping the data and control signals to the reduced number of pins.

9. A media interface as defined in claim 8 wherein the reduced number of pins is 12.

10. A media interface as defined in claim 8 further comprising six input pins for use in either the gigabit media independent interface operation or the ten bit interface operation in which:

a transmit reference clock signal TXC is applied to a first pin in the gigabit media independent interface operation and the ten bit interface operation;

8 bits of data are applied to the second through fifth pins on both edges of a clock cycle during the gigabit media independent interface operation and the ten bit interface operation;

2 bits of data are applied to the sixth pin in the ten bit interface operation; and

,

control signals are applied to the second through fifth pin in the gigabit media independent interface operation.

11. A media interface as defined in claim 8 further comprising six output pins for use in either the gigabit media independent interface operation or the ten bit interface operation in which:

a receive reference clock signal RXC is derived from the received data stream and appears on a first pin in the gigabit media independent interface operation and the ten bit interface operation;

8 bits of data are applied to the second through fifth pins on both edges of a clock cycle during the gigabit media independent interface operation and the ten bit interface operation;

2 bits of data are applied to the sixth pin in the ten bit interface operation; and

, control signals are applied to the second through fifth pin in the gigabit media independent interface operation.

12. Apparatus as defined in claim 8 wherein CRS and COL signals are applied on the same pin.

13. A method of interfacing a media access controller (MAC) and a physical layer device (PHY) to comply with the standards of IEEE 802 for at least one of the gigabit media independent interface and the ten bit interface, and transfer data at a predetermined rate while substantially reducing the required number of input and output pins, said method comprising:

multiplexing data and control signals using both edges of a clock signal having the predetermined rate; and

,

strategically mapping the data and control signals that are normally applied to a predetermined number of pins to a significantly lesser number of pins while still maintaining the operability of the interface.