Shared memory architecture in GPS signal processing

• US 20030088741A1
• Filed: 12/04/2002
• Published: 05/08/2003
• Est. Priority Date: 12/16/1999
• Status: Active Grant

• Current Assignee: CSR plc (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Peng, Leon Kuo-Liang, Falk, Henry D.
• Granted Patent: US 6,930,634 B2
• Time in Patent Office: Days
• US Class Current: 711/146
• CPC Class Codes: G01S 19/24 Acquisition or tracking or demodulation of signals transmitted by the system synchronisation aspects of direct sequence spread spectrum modulation H04B1/7073
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain

Abstract

A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

Claims

1. A shared memory architecture for a receiver system comprising a memory space shared commonly by two or more receiver functions comprising a correlator signal processing, a tracking processing and an application processing unit to minimize memory space requirement.

2. The shared memory architecture of claim 1 wherein the commonly shared memory space functions as a coherent and a noncoherent integration memory for the correlation processing during signal correlation mode while the commonly shared memory space is also used for one or more other receiver processing functions during one or more other receiver operation modes.

3. The shared memory architecture of claim 1 wherein the commonly shared memory space comprises a first memory section and a second memory section, wherein the first memory section functions as a coherent and the second memory section as a noncoherent integration memory for a correlation processing during signal correlation mode while the shared memory space is also used for one or more other receiver processing functions during one or more other receiver operation modes.

4. The shared memory architecture of claim 1 wherein the commonly shared memory space comprises a first memory section used as the system memory for a fast local memory or system cache during tracking or application processing.

5. The shared memory architecture of claim 1 wherein the application processing comprise navigation processing.

6. The shared memory architecture of claim 1 wherein the application processing comprise GPS location processing.

7. The shared memory architecture of claim 1 wherein the application processing comprise wireless networking protocol processing.