Mobile wireless communication device architectures and methods therefor
First Claim
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1. A wireless communication architecture, comprising:
- a virtual channel memory controller;
first and second processor cores coupled to the virtual channel memory controller;
a first synchronous memory device coupled to the virtual channel memory controller by a dedicated first data bus;
a second synchronous memory device coupled to the virtual channel memory controller by a dedicated second data bus;
a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices.
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Abstract
A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second synchronous memory devices are addressed with the shared address bus, and the first and second memory locations are accessed via the first and second data buses, respectively.
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Citations
25 Claims
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1. A wireless communication architecture, comprising:
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a virtual channel memory controller;
first and second processor cores coupled to the virtual channel memory controller;
a first synchronous memory device coupled to the virtual channel memory controller by a dedicated first data bus;
a second synchronous memory device coupled to the virtual channel memory controller by a dedicated second data bus;
a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A virtual channel shared memory architecture, comprising:
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a virtual channel memory controller;
a first synchronous memory device coupled to the virtual channel memory controller by a first data bus;
a second synchronous memory device coupled to the virtual channel memory controller by a second data bus;
a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. - View Dependent Claims (10, 11, 12)
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13. A method in a virtual channel shared memory system architecture, comprising:
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addressing first and second synchronous memory devices with a shared address bus interconnecting the first and second synchronous memory devices and a virtual channel memory controller;
accessing the first synchronous memory device via a first data bus interconnecting the first synchronous memory device and the virtual channel memory controller;
accessing the second synchronous memory device via a second data bus interconnecting the second synchronous memory device and the virtual channel memory controller. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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21. A method in a wireless communication architecture, comprising:
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addressing first and second synchronous memory devices with a shared address bus interconnecting the first and second synchronous memory devices and a virtual channel memory controller;
transferring data between the first synchronous memory device and the virtual channel memory controller on a first data bus;
transferring data between the second synchronous memory device and the virtual channel memory controller on a second data bus. - View Dependent Claims (22, 23, 24, 25)
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Specification