Multi-processor mobile computer system having one processor integrated with a chipset

• US 20030088800A1
• Filed: 11/27/2002
• Published: 05/08/2003
• Est. Priority Date: 12/22/1999
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cai, Zhong-Ning
• Granted Patent: US 6,718,475 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Computer systems having two processors of different clock frequencies and different levels of power consumption. An interface circuit can select one of the two processors to operate at a time to reduce power consumption without compromising the system performance.

Claims

1. A computer system, comprising:

a first processor to operate at a first clock frequency and a first level of power consumption;

a second processor to operate at a second clock frequency and a second level of power consumption, the second clock frequency and the second level of power consumption being respectively less than the first clock frequency and the first level of power consumption;

an interface circuit coupled to the first processor and the second processor, the interface circuit to implement a powersaving mode by selecting one of the first processor and the second processor to operate at a time, the interface circuit to further implement the powersaving mode by turning off electric power to the first processor if the second processor is selected to operate.

2. A computer system as in claim 1, wherein the second processor and the interface circuit are integrated on a single substrate.

3. A computer system as in claim 2, wherein the interface circuit is included in a chipset.

4. A computer system as in claim 3, further comprising a system memory and a graphic controller integrated with the second processor and the chipset on the single substrate.

5. A computer system as in claim 1, the interface circuit to implement the powersaving mode when AC power is not available.

6. A computer system as in claim 1, the interface circuit to further implement the powersaving mode by maintaining power to the second processor when the first processor is selected to operate.

7. A computer system as in claim 1, the interface circuit to further implement the powersaving mode by turning off electric power to the second processor when the first processor is selected to operate.

8. A computer system as in claim 1, the interface circuit to select the first processor to execute one or more instructions when a processing power of the second processor is insufficient to execute the one or more instructions.

9. A method comprising:

determining that a computer system should be in a powersaving mode;

selecting one processor of a first processor and a second processor to operate at a time, the first processor to operate at a first clock frequency and a first power consumption level, the second processor to operate at a second clock frequency and a second power consumption level which are respectively less than the first clock frequency and the first power consumption level; and

turning off electric power to the first processor when the second processor is selected to operate.

10. A method as in claim 9, further comprising:

selecting another processor to operate subsequent to the one processor; and

making data in at least one cache of the one processor available to the another processor after the one processor completes execution of one or more instructions.

11. A method as in claim 10, wherein the data in at least one cache of the one processor is saved to a system memory shared by the one processor and the another processor.

12. A method as in claim 11, further comprising generating an interrupt to command the one processor to save the data in the system memory when the one processor is to be replaced by the another processor.

13. A method as in claim 10, further comprising transferring the data from the one processor directly to the another processor.

14. A method as in claim 9, further comprising:

selecting another processor to operate subsequent to the one processor; and

establishing a communication between the one processor and the another processor to inform CPU states of the one processor to the another processor after the one processor completes execution of one or more instructions.

15. A method as in claim 14, further comprising saving the CPU states of the one processor into a memory accessible to the another processor.

16. A method as in claim 14, further comprising transferring the CPU states of the one processor directly to the another processor.

17. A method as in claim 14, further comprising using a software routine to inform the CPU states of the one processor to the another processor.

18. A computer system, comprising:

a first chip including a first processor to operate at a first clock frequency and a first level of power consumption; and

a second chip separate from said first chip, the second chip including a second processor to operate at a second clock frequency and a second level of power consumption which are respectively less than the first clock frequency and the first level of power consumption, the second chip further including an interface circuit to implement a powersaving mode by selecting one of said first and second processors to operate at a time, the interface circuit to further implement the powersaving mode by turning off electric power to the first processor when the second processor is selected to operate.

19. A computer system as in claim 18, wherein the interface circuit is included in a chipset integrated on the second chip.

20. A computer system as in claim 18, wherein the second chip further comprises a system memory and a graphic controller.

21. A computer system as in claim 18, wherein the second chip further comprises a RAM unit to store CPU states from the first and second processors.