Semiconductor device and method for fabricating the same

• US 20030089906A1
• Filed: 11/13/2002
• Published: 05/15/2003
• Est. Priority Date: 11/13/2001
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ueda, Tetsuzo
• Granted Patent: US 6,861,335 B2
• Time in Patent Office: Days
• US Class Current: 257/55
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: C30B 25/183 being provided with a buffer layer, e.g. a lattice matching layer
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02472 Oxides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 33/025 Physical imperfections, e.g. particular concentration or distribution of impurities
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01S 2301/173 The laser chip comprising special buffer layers, e.g. dislocation prevention or reduction
• CPC Class Codes: H01S 5/0202 Cleaving
• CPC Class Codes: H01S 5/0213 Sapphire, quartz or diamond based substrates
• CPC Class Codes: H01S 5/0215 Bonding to the substrate
• CPC Class Codes: H01S 5/0217 Removal of the substrate
• CPC Class Codes: H01S 5/0218 Substrates comprising semiconducting materials from other groups of the Periodic Table than the materials of the active layer
• CPC Class Codes: H01S 5/320225 polar orientation
• CPC Class Codes: H01S 5/34333 : with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

A spacer layer is formed on a single-crystal substrate and an epitaxially grown layer composed of a group III-V compound semiconductor layer containing a nitride or the like is further formed on the spacer layer. The epitaxially grown layer is adhered to a recipient substrate. The back surface of the single-crystal substrate is irradiated with a light beam such as a laser beam or a bright line spectrum from a mercury vapor lamp such that the epitaxially grown layer and the single-crystal substrate are separated from each other. Since the forbidden band of the spacer layer is smaller than that of the single-crystal substrate, it is possible to separate the thin semiconductor layer from the substrate by decomposing or fusing the spacer layer, while suppressing the occurrence of a crystal defect or a crack in the epitaxially grown layer.

Claims

1. A method for fabricating a semiconductor device having a semiconductor layer formed by epitaxial growth from a single-crystal substrate, the method comprising the steps of:

(a) forming a spacer layer having an optical band gap smaller than an optical band gap of a lowermost portion of the semiconductor layer such that an upper surface of the single-crystal substrate is covered with the spacer layer;

(b) forming the semiconductor layer on the spacer layer; and

(c) irradiating the spacer layer with a light beam having an energy smaller than an optical band gap of the single-crystal substrate and larger than the optical band gap of the spacer layer through a back surface of the single-crystal substrate to separate the semiconductor layer from the single-crystal substrate.

2. The method of claim 1, wherein the step (b) includes forming a compound semiconductor layer containing nitrogen as the semiconductor layer.

3. The method of claim 1, wherein the step (b) includes forming a group III-V compound semiconductor layer as the semiconductor layer.

4. The method of claim 3, wherein

the step (a) includes forming a ZnO layer as the spacer layer and

the step (b) includes composing the lowermost portion of the semiconductor layer of a group III-V compound material containing nitrogen and having an optical band gap larger than an optical band gap of the ZnO layer.

5. The method of claim 1, wherein

the step (a) includes forming, as the spacer layer, a group III-V compound semiconductor layer containing nitrogen and

the step (b) includes composing the lowermost portion of the semiconductor layer of a group III-V compound semiconductor layer containing nitrogen and having an optical band gap larger than the optical band gap of the spacer layer.

6. The method of claim 5, wherein

the step (a) includes forming an In_xGa₁₋

xN layer (0<

x≦

1) as the spacer layer and

the step (b) includes composing the lowermost portion of the semiconductor layer of an Al_yGa<sub>1−

y</sub>N layer (0<

y≦

1).

7. The method of claim 5, wherein

the step (a) includes forming a GaN layer as the spacer layer and

the step (b) includes composing the lowermost portion of the semiconductor layer of an Al_yGa₁₋

yN layer (0<

y≦

1).

8. The method of claim 7, wherein

the step (a) includes forming a GaN layer as the spacer layer and

the step (b) includes adjusting a thickness of the semiconductor layer to a range not less than 0.5 μ

m and less than 4 μ

m.

9. The method of claim 1, further comprising, after the step (a) and prior to the step (b), the step of:

forming, on the spacer layer, a multilayer portion composed of a plurality of thin films stacked in layers to have gradually varying compositions, wherein

the step (b) includes forming the semiconductor layer on the multilayer portion.

10. The method of claim 9, wherein the multilayer portion is a multiple quantum well layer composed of alternately stacked quantum well layers and barrier layers.

11. The method of claim 1, wherein the step (b) includes the substeps of:

(b1) forming a plurality of covering portions covering the spacer layer in mutually spaced apart relation; and

(b2) forming the semiconductor layer such that the spacer layer and the plurality of covering portions are covered with the semiconductor layer.

12. The method of claim 11, wherein the substep (b2) includes the steps of:

prior to the substep (b1), forming, in a part of the semiconductor layer covering the spacer layer, the plurality of covering portions in mutually spaced apart relation; and

after the substep (b1), forming a remaining part of the semiconductor layer through a space between the covering portions.

13. The method of claim 11, wherein the substep (b2) includes forming the covering portions composed of a multilayer insulating film or a metal film.

14. The method of claim 11, wherein the substep (b2) includes forming the covering portions composed of a material lower in thermal conductivity than the spacer layer.

15. The method of claim 1, wherein the step (c) includes performing the irradiation with the light beam having an energy smaller than the optical band gap of the lowermost portion of the semiconductor layer.

16. The method of claim 1, further comprising, prior to the step (a), the step of:

forming, on the single-crystal substrate, a buffer layer having an optical band gap larger than the energy of the light beam used for the irradiation in the step (c) such that the buffer layer reduces distortion resulting from a lattice mismatch between the spacer layer and the single-crystal substrate in the step (c), wherein

the step (a) includes forming the spacer layer on the buffer layer.

17. The method of claim 16, wherein the step of forming the buffer layer includes forming, as the buffer layer, an AlN buffer layer having a thickness in the range of 0.5 μ

m to 2 μ

m.

18. The method of claim 1, further comprising, prior to the step (a), the step of:

forming, on the single-crystal substrate, an AlN buffer layer having a thickness of 0.5 μ

m or more, wherein

the step (a) includes forming an In_xGa<sub>1−

x</sub>N layer (0<

x≦

1) or a GaN layer as the spacer layer and

the step (b) includes forming the semiconductor layer on the spacer layer such that the lowermost portion of the semiconductor layer is composed of an Al_yGa<sub>1−

y</sub>N layer (0<

y ≦

1).

19. The method of claim 1, wherein the step (c) includes performing the irradiation with the light beam from a laser oscillating pulsatively.

20. The method of claim 1, wherein

the step (c) includes irradiating the back surface of the single-crystal substrate with a bright line spectrum from a mercury vapor lamp.

21. The method of claim 1, wherein

the step (c) includes heating the single-crystal substrate.

22. The method of claim 21, wherein a temperature to which the single-crystal substrate is heated in the step (c) is in the range of 400°

C. to 750°

C.

23. The method of claim 1, wherein the step (c) includes performing the irradiation with the light beam such that an optical flux from a light source scans the entire surface of the single-crystal substrate.

24. The method of claim 1, wherein a substrate selected from a sapphire substrate, an SiC substrate, an MgO substrate, an LiGaO₂ substrate, an LiGa_xAl₁₋

xO₂ (0≦

x≦

1) mixed crystal substrate, and an LiAlO₂ substrate is used as the single-crystal substrate.

25. The method of claim 1, further comprising, after the step (b) and prior to the step (c), the step of:

fixing, onto the semiconductor layer, a recipient substrate composed of a material different from a material composing the semiconductor layer, wherein

the step (c) includes bowinging the semiconductor layer from the single-crystal substrate to the recipient substrate.

26. The method of claim 1, further comprising, after the step (c), the step of:

fixing, onto the semiconductor layer, a recipient substrate composed of a material different from a material composing the semiconductor layer and transferring the semiconductor layer from the single-crystal substrate to the recipient substrate.

27. The method of claim 25, wherein a substrate selected from an Si substrate, a GaAs substrate, a GaP substrate, and an InP substrate is used as the recipient substrate.

28. A method for fabricating a semiconductor device, the method comprising the steps of:

(a) forming an AlN buffer layer having a thickness of 0.5 μ

m or more on an single-crystal substrate;

(b) forming a semiconductor layer covering the AlN buffer layer and having a lowermost portion composed of an Al_yGa<sub>1−

y</sub>N layer (0≦

y≦

1); and

(c) irradiating the semiconductor layer with a light beam having an energy smaller than an optical band gap of the AlN buffer layer and larger than an optical band gap of the lowermost portion of the semiconductor layer through a back surface of the single-crystal layer to separate the semiconductor layer from the single-crystal substrate.

29. A method for fabricating a semiconductor device having a semiconductor layer formed by epitaxial growth from a single-crystal substrate, the method comprising the steps of:

(a) forming a multilayer portion for preventing extension of a defect such that an upper surface of the single-crystal substrate is covered therewith, the multilayer portion being composed of a plurality of thin films stacked in layers to have gradually varying compositions; and

(b) forming the semiconductor layer on the multilayer portion.

30. The method of claim 29, wherein

the step (a) includes forming the multilayer portion by alternately stacking in layers two thin films having different compositions.

31. The method of claim 29, wherein

the step (a) includes forming the multilayer portion having a multiple quantum well structure in which the plurality of thin films are quantum well layers and barrier layers.

32. The method of claim 31, wherein

the step (a) includes doping either the quantum well layers or the barrier layers with a dopant at such a high concentration as to allow carriers to spread out upon application of an ON voltage.

33. A semiconductor device comprising:

a substrate;

a semiconductor layer provided on the substrate and including an active layer serving as a light-emitting region; and

a multiple quantum well layer provided on the semiconductor layer and composed of quantum well layers and barrier layers which are alternately stacked.

34. The device of claim 33, wherein either the quantum well layers or the barrier layers contain a dopant at such a high concentration as to allow carriers to spread out upon application of an ON voltage.