Active matrix semiconductor device

• US 20030089916A1
• Filed: 11/05/2002
• Published: 05/15/2003
• Est. Priority Date: 11/14/2001
• Status: Active Grant

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Matsumoto, Shoichiro
• Granted Patent: US 7,084,862 B2
• Time in Patent Office: Days
• US Class Current: 257/88
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0278 Details of driving circuits arranged to drive both scan and data electrodes
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Abstract

Provided is a semiconductor device, including a pixel part or a sensor part, capable of reducing the size of a connector part connecting the semiconductor device with an external IC in correspondence to miniaturization of the semiconductor device also when the semiconductor device is miniaturized. In this semiconductor device, a pixel part or a sensor part arranged in the form of a matrix, a scanning system driving circuit driving a gate line, a data system driving circuit driving a drain line and a scanning system control signal generation circuit generating a control signal for the scanning system driving circuit are formed on an identical substrate. Thus, a scanning system control signal is generated in the substrate, whereby the number of external input signals is reduced. Therefore, the number of signal lines wired to the connector part connected to the semiconductor device is reduced, whereby the size of the connector part can be reduced.

Claims

1. A semiconductor device including:

a pixel part or a sensor part arranged in the form of a matrix;

a scanning system driving circuit driving a gate line;

a data system driving circuit driving a drain line; and

a scanning system control signal generation circuit generating a control signal for said scanning system driving circuit,

formed on an identical substrate.

2. The semiconductor device according to claim 1, wherein

said scanning system control signal generation circuit includes:

a scanning system synchronizing signal generation circuit generating a scanning system synchronizing signal on the basis of a reset signal and a signal indicating that data system scanning reaches the final stage, and

a scanning system start signal generation circuit generating a start signal on the basis of at least any of said reset signal, said scanning system synchronizing signal, a signal related to a gate line activation signal rising second and a signal indicating that gate system scanning reaches the final stage.

3. The semiconductor device according to claim 1, wherein

a data system control signal generation circuit generating a control signal for said data system driving circuit is at least partially formed on said identical substrate.

4. The semiconductor device according to claim 3, wherein

said data system control signal generation circuit includes:

a basic clock generation circuit for generating a basic clock for said control signal,

a data system synchronizing signal generation circuit generating a data system synchronizing signal on the basis of said basic clock, and

a data system start signal generation circuit generating a start signal on the basis of said basic clock and said data system synchronizing signal, and

at least said data system synchronizing signal generation circuit and said data system start signal generation circuit are formed on said identical substrate.

5. The semiconductor device according to claim 4, wherein

said basic clock generation circuit is also formed on said identical substrate in addition to said data system synchronizing signal generation circuit and said data system start signal generation circuit.

6. The semiconductor device according to claim 5, wherein

said data system synchronizing signal generation circuit has a function of dividing the output cycle of said basic clock generation circuit to a prescribed magnification.

7. The semiconductor device according to claim 6, wherein

said data system synchronizing signal generation circuit includes a plurality of inverters to have an odd-stage cycle.

8. The semiconductor device according to claim 1, wherein

a first level conversion circuit for converting the voltage level of an externally input reset signal is further formed on said identical substrate.

9. The semiconductor device according to claim 8, wherein

a second level conversion circuit for converting the voltage level of an externally input data system start signal is further formed on said identical substrate.

10. The semiconductor device according to claim 9, wherein

a third level conversion circuit for converting the voltage level of an externally input data system synchronizing signal is further formed on said identical substrate.

11. A display including:

a pixel part arranged in the form of a matrix;

a scanning system driving circuit driving a gate line;

a data system driving circuit driving a drain line; and

a scanning system control signal generation circuit generating a control signal for said scanning system driving circuit,

formed on an identical substrate.

12. The display according to claim 11, wherein

said scanning system control signal generation circuit includes:

a scanning system synchronizing signal generation circuit generating a scanning system synchronizing signal on the basis of a reset signal and a signal indicating that data system scanning reaches the final stage, and

a scanning system start signal generation circuit generating a start signal on the basis of at least any of said reset signal, said scanning system synchronizing signal, a signal related to a gate line activation signal rising second and a signal indicating that gate system scanning reaches the final stage.

13. The display according to claim 11, wherein

a data system control signal generation circuit generating a control signal for said data system driving circuit is at least partially formed on said identical substrate.

14. The display according to claim 13, wherein

said data system control signal generation circuit includes:

a basic clock generation circuit for generating a basic clock for said control signal,

a data system synchronizing signal generation circuit generating a data system synchronizing signal on the basis of said basic clock, and

a data system start signal generation circuit generating a start signal on the basis of said basic clock and said data system synchronizing signal, and

at least said data system synchronizing signal generation circuit and said data system start signal generation circuit are formed on said identical substrate.

15. The display according to claim 14, wherein

said basic clock generation circuit is also formed on said identical substrate in addition to said data system synchronizing signal generation circuit and said data system start signal generation circuit.

16. A signal detector including:

a sensor part arranged in the form of a matrix;

a scanning system driving circuit driving a gate line;

a data system driving circuit driving a drain line; and

a scanning system control signal generation circuit generating a control signal for said scanning system driving circuit,

formed on an identical substrate.

17. The signal detector according to claim 16, wherein

said scanning system control signal generation circuit includes:

a scanning system synchronizing signal generation circuit generating a scanning system synchronizing signal on the basis of a reset signal and a signal indicating that data system scanning reaches the final stage, and

a scanning system start signal generation circuit generating a start signal on the basis of at least any of said reset signal, said scanning system synchronizing signal, a signal related to a gate line activation signal rising second and a signal indicating that gate system scanning reaches the final stage.

18. The signal detector according to claim 16, wherein

a data system control signal generation circuit generating a control signal for said data system driving circuit is at least partially formed on said identical substrate.

19. The signal detector according to claim 18, wherein

said data system control signal generation circuit includes:

a basic clock generation circuit for generating a basic clock for said control signal,

a data system synchronizing signal generation circuit generating a data system synchronizing signal on the basis of said basic clock, and

a data system start signal generation circuit generating a start signal on the basis of said basic clock and said data system synchronizing signal, and

at least said data system synchronizing signal generation circuit and said data system start signal generation circuit are formed on said identical substrate.

20. The signal detector according to claim 19, wherein

said basic clock generation circuit is also formed on said identical substrate in addition to said data system synchronizing signal generation circuit and said data system start signal generation circuit.