Scalable gate and storage dielectric
First Claim
1. A gate dielectric stack used in integrated circuit devices, said stack comprising:
- a substrate;
a high K gate dielectric having a first and a second surface, said second surface forming an interface with said substrate, said interface having a charge no greater than about 3e+10 fundamental charge units per cm;
a gate; and
a passivated overlayer having a first and a second surface, said second surface of said passivated overlayer forming a first chemically inert interface with said first surface of said high K gate dielectric, said first surface of said passivated overlayer forming a second chemically inert interface with said gate;
wherein said K is a dielectric constant.
8 Assignments
0 Petitions
Accused Products
Abstract
Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with a substrate or second plate. This improves dielectric system reliability and uniformity and permits greater scalability, dielectric interface compatibility, structural stability, charge control, and stoichiometric reproducibility. Furthermore, etch selectivity, low leakage current, uniform dielectric breakdown, and improved high temperature chemical passivity also result.
-
Citations
86 Claims
-
1. A gate dielectric stack used in integrated circuit devices, said stack comprising:
-
a substrate;
a high K gate dielectric having a first and a second surface, said second surface forming an interface with said substrate, said interface having a charge no greater than about 3e+10 fundamental charge units per cm;
a gate; and
a passivated overlayer having a first and a second surface, said second surface of said passivated overlayer forming a first chemically inert interface with said first surface of said high K gate dielectric, said first surface of said passivated overlayer forming a second chemically inert interface with said gate;
whereinsaid K is a dielectric constant. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A storage dielectric stack used in integrated circuit devices, said stack comprising:
-
a first plate;
a high K storage dielectric having a first and a second surface, said second surface forming an interface with said first plate, said interface having a charge no greater than about 3e+10 fundamental charge units per cm2;
a second plate; and
a passivated overlayer having a first and a second surface, said second surface of said passivated overlayer forming a first chemically inert interface with said first surface of said high K storage dielectric, said first surface of said passivated overlayer forming a second chemically inert interface with said second plate;
whereinsaid K is a dielectric constant. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
-
-
27. A gate dielectric stack used in integrated circuit devices, said stack comprising:
-
a substrate;
an alumina gate dielectric having a first and a second surface, said second surface forming an interface with the substrate;
a gate; and
a silicon-rich-nitride overlayer having a first and a second surface, said second surface of said silicon-rich-nitride overlayer forming a first chemically inert interface with said first surface of said alumina gate dielectric, said first surface of said silicon-rich-nitride overlayer forming a second chemically inert interface with said gate. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34)
-
-
35. A storage dielectric stack used in integrated circuit devices, said stack comprising:
-
a first plate;
an alumina storage dielectric having a first and a second surface, said second surface forming an interface with said first plate;
a second plate; and
a silicon-rich-nitride overlayer having a first and a second surface, said second surface of said silicon-rich-nitride overlayer forming a first chemically inert interface with said first surface of said alumina storage dielectric, said first surface of said silicon-rich-nitride overlayer forming a second chemically inert interface with said second plate. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42)
-
-
43. A gate dielectric stack used in integrated circuit devices, said stack comprising:
-
a substrate;
an alumina gate dielectric having a first and a second surface, said second surface forming an interface with said substrate, said alumina gate dielectric having a K in the range of about 11 to about 12, said K being a dielectric constant, said interface having a charge no greater than about 3e+10 fundamental charge units per cm2;
a gate; and
a silicon-rich-nitride overlayer having a first and a second surface, said second surface of said silicon-rich-nitride overlayer forming a first chemically inert interface with said first surface of said alumina gate dielectric, said first surface of said silicon-rich-nitride overlayer forming a second chemically inert interface with said gate, said silicon-rich-nitride overlayer having a refractive index greater than or equal to about 2.5, said silicon-rich-nitride layer having a thickness in the range of about 0.5 to about 3 nm. - View Dependent Claims (44, 45)
-
-
46. A storage dielectric stack used in integrated circuits, said stack comprising:
-
a first plate;
an alumina storage dielectric having a first and a second surface, said second surface forming an interface with said first plate, said interface having a charge no greater than about 3e+10 fundamental charge units per cm2;
a second plate; and
a silicon-rich-nitride overlayer having a first and a second surface, said second surface of said silicon-rich-nitride overlayer forming a first chemically inert interface with said first surface of said alumina storage dielectric, said first surface of said silicon-rich-nitride overlayer forming a second chemically inert interface with said second plate, said silicon-rich-nitride overlayer having a refractive index greater than or equal to about 2.5, said silicon-rich-nitride layer having a thickness in the range of about 0.5 to about 3 nm. - View Dependent Claims (47, 48)
-
-
49. A method of fabricating a gate dielectric stack for a field effect transistor, said method comprising:
-
removing native SixOyHz from a region of a substrate;
depositing on said region a layer of metal that forms a high K dielectric material when oxidized;
oxidizing said layer to form said high K dielectric material;
depositing a passivated overlayer on said layer;
depositing a gate on said passivated overlayer; and
depositing a gate electrode on said gate;
whereinsaid K is a dielectric constant. - View Dependent Claims (50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62)
-
-
63. A method of fabricating a storage dielectric stack for an integrated circuit device, said method comprising:
-
removing native SixOyHz from a region of a first plate;
depositing on said region a layer of metal that forms a high K dielectric material when oxidized;
oxidizing said layer to form said high K dielectric material;
depositing a passivated overlayer on said layer; and
depositing a second plate on said passivated overlayer;
whereinsaid K is a dielectric constant. - View Dependent Claims (64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76)
-
-
77. A method of fabricating a gate dielectric stack for a field effect transistor, said method comprising:
-
removing native SixOyHz from a region of a substrate;
depositing a layer of aluminum having a thickness of less than about 3 nm on said region;
oxidizing said layer of aluminum to form a layer of alumina;
depositing a passivated overlayer of silicon-rich-nitride on said layer of alumina by a low pressure plasma enhanced chemical vapor deposition process, said passivated overlayer having a thickness of about 0.5 to about 3 nm, said passivated overlayer having a refractive index no less than about 2.5, said low pressure chemical vapor deposition process using SiH4 or SiH2Cl2, NH3, and nitrogen such that the ratio of SiH4 or SiH2Cl2 to NH3 is no less than about 15;
depositing a gate on said passivated overlayer; and
depositing a gate electrode on said gate. - View Dependent Claims (78, 79, 80, 81)
-
-
82. A method of fabricating a storage dielectric stack for an integrated circuit device, said method comprising:
-
removing native SixOyHz from a region of a first plate;
depositing a layer of aluminum having a thickness of less than about 3 nm on said region;
oxidizing said layer of aluminum to form a layer of alumina;
depositing a passivated overlayer of silicon-rich-nitride on said layer of alumina by a low pressure plasma enhanced chemical vapor deposition process, said passivated overlayer having a thickness of about 0.5 to about 3 nm, said passivated overlayer having a refractive index no less than about 2.5, said low pressure chemical vapor deposition process using SiH4 or SiH2Cl2, NH3, and nitrogen such that the ratio of SiH4 or SiH2Cl2 to NH3 is no less than about 15; and
depositing a second plate on said passivated overlayer. - View Dependent Claims (83, 84, 85, 86)
-
Specification