Pixel buffer circuits for implementing improved methods of displaying grey-scale or color images

• US 20030090478A1
• Filed: 09/17/2002
• Published: 05/15/2003
• Est. Priority Date: 07/20/1995
• Status: Abandoned Application

• Current Assignee: The Board of Regents of the University of Colorado (University of Colorado System)
• Original Assignee: The Board of Regents of the University of Colorado (University of Colorado System)
• Inventors: McKnight, Douglas J.
• Application Number:
  US10/244,379
• Publication Number:
  US 20030090478A1
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G06T 3/40 Scaling of whole images or parts thereof, e.g. expanding or contracting
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0823 used to establish symmetry in driving, e.g. with polarity inversion
• CPC Class Codes: G09G 2300/0828 forming a digital to analog [D/A] conversion circuit
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2320/0266 Reduction of sub-frame artefacts
• CPC Class Codes: G09G 2320/0633 by amplitude modulation of the brightness of the illumination source
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2033 with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
• CPC Class Codes: G09G 3/2037 with specific control of sub-frames corresponding to the least significant bits
• CPC Class Codes: G09G 3/3406 Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 : the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

A device such as a display device or a spatial light modulator can store pixel data in a plurality of small circuit coupled to pixel mirrors and simultaneously drive these pixel mirrors a frame at a time. This device is particularly beneficial for implementing improved image quality techniques which can convert binary images to grey-scale images and/or separate red, green and blue images into color images and displaying those images using the natural process of integration which occurs when a person views images at sufficiently high rates.

Claims

1. A device, comprising:

a substrate having a first surface;

a plurality of driving electrodes arranged on said first surface of the substrate; and

a plurality of means arranged on said substrate and respectively coupled to said plurality of driving electrodes, for receiving and storing image data and for driving said plurality of driving electrodes a frame at a time synchronous with a switching-signal.

2. The device as claimed in claim 1, wherein each of said plurality of means comprises:

a first switch coupled to a gate signal and a data line for receiving a pixel datum of said image data and outputting said pixel datum in accordance with said gate signal;

a first inverter coupled to said first switch for receiving said pixel datum;

a second switch coupled to a clock signal and said first inverter; and

a second inverter coupled to said switch and to a respective one of said plurality of driving electrodes, wherein said pixel datum is transmitted from said first inverter to said second inverter synchronous with said clock signal, and outputs said pixel datum to said respective one of the plurality of driving electrodes.

3. The device as claimed in claim 1, further comprising a liquid crystal layer arranged on said first surface.

4. The display device as claimed in claim 3, further comprising a window arranged on said liquid crystal layer, wherein said plurality of means comprises a plurality of storage elements capable of approximately simultaneously outputting said image data to said driving electrodes which drive said liquid crystal layer to yield an image.

5. The display device as claimed in claim 2, wherein said first switch comprises a first transistor and said second switch comprises a second transistor.

7. The display device as claimed in claim 2, wherein said first switch comprises a first pair of FETs and said second switch comprises a second pair of FET5.

8. The device as claimed in claim 2, further comprising a liquid crystal layer arranged on said first surface.

9. The device as claimed in claim 1, wherein each of said plurality of means comprises a first switch coupled to a gate signal and a data line for receiving a pixel of datum of said data and outputting said pixel datum in accordance with said gate signal.

10. The device as claimed in claim 9, wherein each of said plurality of means further comprises a first inverter coupled to said first switch for receiving said pixel datum.

11. The device as claimed in claim 10, wherein each of said plurality of means further comprises a second switch coupled to a clock signal and said first inverter.

12. The device as claimed in claim 11, wherein each said plurality of means further comprises a second inverter which receives and outputs said pixel datum to a respective one of the plurality of driving electrodes.

13. The device as claimed in claim 1, wherein each of said plurality of means comprises:

a first switch coupled to a gate signal and a data line for receiving a pixel datum of said data and outputting said pixel datum in accordance with said gate signal;

a capacitance means coupled to said first switch for receiving and storing said pixel datum;

a second switch coupled to a clock signal and said capacitance means; and

an inverter coupled to said switch and to a respective one of said plurality of driving electrodes, wherein said pixel data is transmitted from said capacitor means to said inverter synchronous with said clock signal, and which outputs said pixel data to said respective one of the plurality of driving electrodes.

14. The device as claimed in claim 13, wherein said capacitance means comprises a capacitor.

15. The device as claimed in claim 13, further comprising a liquid crystal layer arranged on said first surface.

16. The device as claimed in claim 1, further comprising a first switch coupled to a gate signal and a data line for receiving a pixel datum of said data and outputting said pixel datum in accordance with said gate signal.

17. The device as claimed in claim 16, further comprising capacitance means coupled to said first switch for receiving and storing said pixel datum.

18. The device as claimed in claim 17, further comprising a second search coupled to a clock signal and said capacitance means.

19. The device as claimed in claim 18, further comprising a second switch coupled to a clock signal and said capacitance means.

20. The device as claimed in claim 19, further comprising an inverter which receives and outputs a pixel datum to said respective one of the plurality of driving electrodes.

21. The device as claimed in claim 1, wherein said plurality of means receives image data comprising a series of subframes.

22. The device as claimed in claim 21, wherein said plurality of means receives image data comprising a series of color subframes to be displayed in series at sufficiently high frame rates to produce color integration of images to an observer.

23. The device as-claimed in claim 21, wherein said plurality of means receives image data comprising a series of binary subframes to be displayed in series at sufficiently high frame rates to produce grey-scale integration of images to an observer.

24. The device as claimed in claim 1, wherein said substrate comprises a spatial light modulator which is driven by said plurality of driving electrodes.

25. The device as claimed in claim 1, further comprising a liquid crystal layer arranged on said first surface which is driven by said plurality of driving electrodes.

36. The device as claimed in claim 21, wherein said plurality of means receives image data comprising a series of analog color subframes.

37. The device as claimed in claim 22, wherein said plurality of means receives image data comprising a series of binary color subframes.

38. The device as claimed in claim 9, wherein said pixel datum comprises an analog quantity.

39. The device as claimed in claim 10, wherein said first inverter comprises a voltage limiting transistor and said pixel datum comprises an analog quantity.

6. The display device as claimed in chain 5, wherein said first and second transistors are FETs.

26. A device, comprising:

a substrate having a first surface;

a plurality of driving electrodes arranged on said first surface of the substrate; and

a plurality of circuits arranged on said substrate and respectively coupled to said plurality of driving electrodes, for receiving and storing image data and driving said plurality of driving electrodes a frame at a time synchronous with a switching signal.

27. The device as claimed in claim 26, wherein each of said plurality of circuits comprises:

a first switch coupled to a gate signal and a data line for receiving a pixel datum of said image data and outputting said pixel datum in accordance with said gate signal;

a first inverter coupled to said first switch for receiving said pixel datum;

a second switch coupled to a clock signal and said first inverter; and

a second inverter coupled to said switch and to a respective one of said plurality of driving electrodes, wherein said pixel datum is transmitted from said first inverter to said second inverter synchronous with said clock signal, and outputs said pixel datum to said respective one of the plurality of driving electrodes.

28. A method for displaying a color image on a display unit with a plurality of pixels, comprising the steps of:

receiving a Red frame, a Green frame, and a Blue frame comprising the color image to be displayed within a first time period corresponding to a first frame display rate; and

repeatedly and interspersedly displaying said Red frame, said Green frame and said Blue frame within the first time period at a higher rate than said first frame display rate.

29. The method for displaying a color image as claimed in claim 28, wherein said repeatedly and interspersedly displaying step comprises interspersedly displaying said Red frame, said Green frame and said Blue frame two times each, within said first time period.

30. The method for displaying a color image as claimed in claim 28, wherein said repeatedly and interspersedly displaying step comprises interspersedly displaying said Red frame, said Green frame and said Blue frame three times each, within said first time period.

31. The method for displaying a color image as claimed in claim 28, wherein said repeatedly and interspersedly displaying step comprises interspersedly displaying said Red frame, said Green frame and said Blue frame N times each, within said first time period, where N is an integer which is greater than or equal to two.

32. The method for displaying a color image as claimed in claim 28, wherein said receiving step comprises receiving the Red frame, Green frame, and Blue frame comprising the color image to be displayed within a first time period which is less than or equal to about {fraction (1/30)} of a second.

33. The method for displaying a color image as claimed in claim 28, further comprising repeating said receiving step followed by said repeatedly displaying step for a subsequent color image.

34. The method for displaying a color image as claimed in claim 28, further comprising repeating said receiving step followed by said repeatedly displaying step for each color image within a series of subsequent color images.

35. The method for displaying a color image as claimed in claim 28, wherein said repeatedly and interspersedly displaying step comprises repeatedly and interspersedly displaying said Red frame, said Green frame, and said Blue frame in any order.

40. A device, comprising:

a substrate having a first surface;

a plurality of driving electrodes arranged on said first surface of the substrate; and

a plurality of circuits arranged on said substrate and respectively coupled to said plurality of driving electrodes for receiving and storing data, wherein each of said plurality of circuits comprises at least two storage means for receiving and storing data for a respective one of said plurality of driving electrodes, said plurality of circuits driving said plurality of driving electrodes synchronous with a switching signal.

41. The device as claimed in claim 40, wherein each of said plurality of circuits comprises at least three storage means for receiving and storing data for a respective one of said plurality of driving electrodes.

42. The device as claimed in claim 40, wherein said data comprise analog image data.

43. The device as claimed in claim 40, wherein said data comprise binary image data.

44. The device as claimed in claim 42, wherein said analog image data comprises analog color image data.

45. The device as claimed in claim 42, wherein said binary image data comprises analog color image data.

46. The device as claimed in claim 41, wherein said image data comprises color image data and each of said three storage means stores a respective Red datum, Green datum and Blue datum.