Phase and frequency drift and jitter compensation in a distributed telecommunications switch

• US 20030091035A1
• Filed: 05/24/2002
• Published: 05/15/2003
• Est. Priority Date: 11/21/2000
• Status: Active Grant

• Current Assignee: F Poszat Hu LLC (Intellectual Ventures LLC), Transwitch Corporation
• Original Assignee: Transwitch Corporation
• Inventors: Zhovnirovsky, Igor, Roy, Subhash C., Renault, Michael M., Toebes, David K., Benoit, Steven E.
• Granted Patent: US 7,463,626 B2
• Time in Patent Office: Days
• US Class Current: 370/353
• CPC Class Codes: H04J 2203/0025 Peripheral units
• CPC Class Codes: H04J 2203/0026 Physical details
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04L 12/6402 Hybrid switching fabrics
• CPC Class Codes: H04L 2012/6413 Switch peripheries
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

Methods and apparatus for phase and frequency drift and jitter compensation in a distributed switch which carries both TDM and packet data are disclosed. The methods include the insertion of programmable fill times at different stages of the switch to allow buffers to fill, driving service processors (line cards) with different clocks and synchronizing the service processors (line cards) to the switch fabric, providing redundant switch fabric clocks and methods for automatically substituting one of the redundant clocks for a clock which fails, providing redundant switch fabrics each having a different clock and methods for automatically substituting one switch fabric for the other when one fails. The apparatus of the invention includes a plurality of service processors (line cards), switch elements and clock generators. An exemplary clock generator based on an FPGA is also disclosed.

Claims

1. A method for arbitrating bandwidth in a communications switch, comprising:

a) generating a repeating data frame having a plurality of rows;

b) making requests during row N for space in row N+1;

c) buffering a predetermined number of requests; and

d) granting one or more of the buffered requests based on priority.

2. A method according to claim 1, wherein:

said step of buffering comprises buffering a predetermined even number of requests.

3. A method according to claim 1, wherein:

x bits of requests are interleaved with y bits of data, and

said step of buffering includes setting a buffer fill time to a multiple of x+y bits.

4. A method according to claim 1, wherein:

said step of buffering is performed at each stage of the switch.

5. A method according to claim 4, wherein:

the same number of requests are buffered at each stage of the switch.

6. A communications switch, comprising:

a) a plurality of service processors (line cards), each having a local clock generator;

b) a first switch fabric having a first central clock generator; and

c) means for synchronizing each of the local clock generators with the first central clock generator.

7. A switch according to claim 6, wherein:

said means for synchronizing includes

means for transmitting a framing pattern from the each of the service processors (line cards) to the first switch fabric,

means for comparing the framing pattern with the first central clock generator to determine a clock offset for each of said service processors (line cards),

means for transmitting the respective clock offset to each of said service processors (line cards), and

means for adjusting each of said local clocks based on the respective clock offset.

8. A switch according to claim 6, further comprising:

d) a second switch fabric having a second central clock generator; and

e) means for synchronizing said first and second central clock generators.

9. A clock generator for use with another clock generator coupled to the same clock bus:

a) a clock signal source;

b) a switch coupled to said clock signal source and to the clock bus;

c) monitoring means for monitoring the clock bus, said monitoring means coupled to said switch means, wherein

said switch means couples said clock signal source to the clock bus when said monitoring means indicates the absence of a clock signal on the clock bus.

10. A clock generator according to claim 9, further comprising:

d) signalling means couplable to the other clock generator for signalling that said clock signal source is coupled to the clock bus.

11. A synchronizable clock generator for use with another clock generator having a master clock signal, comprising:

a) an adjustable slave clock signal source;

b) comparison means coupled to said adjustable slave clock signal source and to the master clock signal, wherein

said comparison means samples the slave clock signal during the master clock signal to determine the phase difference between the slave clock signal and the master clock signals.