A COMMUNICATION SYSTEM FOR DRIVING PAIRS OF TWISTED PAIR LINKS

• US 20030091056A1
• Filed: 09/19/2002
• Published: 05/15/2003
• Est. Priority Date: 07/11/1996
• Status: Active Grant

• Current Assignee: 4 Links Limited
• Original Assignee: 4 Links Limited
• Inventors: Paul Hulme Walker, Christopher, Michael Cook, Barry
• Granted Patent: US 7,123,578 B2
• Time in Patent Office: Days
• US Class Current: 370/419
• CPC Class Codes: H03M 5/16 the pulses having three levels
• CPC Class Codes: H04B 3/02 Details
• CPC Class Codes: H04L 25/02 Details ; arrangements for supplying electrical power along data transmission lines systems for transmitting signals via power distribution lines H04B3/54
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes
• CPC Class Codes: H04L 5/20 using different combinations of lines, e.g. phantom working

Abstract

A communications system includes tow high speed communication links formed by pairs of transformers at either end thereof. A phantom circuit formed by the pairs of transformers is used to distribute power to devices connected to the high speed links. In transmission part of a communication system, data is transmitted under the control of a continuously variable frequency clock. The transmission is on parallel data-strobe links, and the receive includes circuitry to identify on which parallel the data signal is preset. A method and circuitry is provided for transmitting and receiving dc balanced data strobe signals.

Claims

1. A communications interface comprising:

output circuitry for providing a data signal for transmittal under control of a spread spectrum transmit clock signal; and

a clock source for generating the spectrum transmit clock signal which is continuously variable between upper and lower frequency values.

2. The communications interface of claim 1, wherein

the output circuitry is operable to provide two parallel outputs, one parallel output being said data signal, and another parallel output being a strobe signal and including strobe generation circuitry, wherein

the data signal comprises a serial bit pattern and the strobe generation circuitry generates the strobe signal such that the strobe signal has signal transitions only at bit boundaries where there is no transition on the data signal, the strobe generation circuitry being controlled by a clock signal such that for each clock pulse where there is no signal transition in the data signal a signal transition is generated in the strobe signal.

3. The communications interface of claim 1, said communications interface having data transmission circuitry comprising:

input circuitry for receiving said data signal, said data signal being a binary data signal;

strobe generation circuitry for generating a binary strobe signal, and having signal transitions only at bit boundaries where there is no transition on a parallel binary data signal; and

encoding circuitry for encoding the binary data and strobe signals into respective ternary dc balanced signals;

wherein said output circuitry is operable to transmit ternary encoded data and strobe signals.

4. The communications interface of claim 3, wherein the input circuitry receives n binary bits for transmittal and the data transmission circuitry further comprises:

bit generation circuitry for generating a flag bit associated with the n binary bits;

addition circuitry for adding the flag bit to the n binary bits to form a binary code-word;

calculation circuitry for calculating a running digital sum of successively formed binary code-words; and

inversion circuitry for inverting the n binary bits of data in a code-word that is dependent upon a current running digital sum and for setting the flag bit to indicate inverted data and outputting successive code-words as the binary data signal.

5. The communications interface of claim 4, wherein the data transmission circuitry further comprises calculation circuitry for calculating a disparity of a code-word, wherein if the disparity of a code-word is zero data therein is not inverted.

6. The communications interface of claim 3 having data transmission circuitry, wherein the bit generation circuitry further generates a parity bit and the addition circuitry further adds the parity bit to the n binary bits and the flag bit to form a n+2 binary code-word.

7. The communications interface of claim 3 wherein the data transmission circuitry further comprises control circuitry for controlling the inversion circuitry to invert data in a code-word that is dependent upon a running digital sum at code-word boundaries.

8. The communications interface of claim 3 wherein the data transmission circuitry further comprises substitution storage means for storing those code-words having zero disparity and their flag bits set to indicate inversion of data therein, such code-words being used to substitute for code-words which increase a running digital sum at code-word boundaries or a run length of the data signal.