Data clock regenerating apparatus

• US 20030091138A1
• Filed: 03/13/2002
• Published: 05/15/2003
• Est. Priority Date: 11/14/2001
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tagami, Hitoyuki
• Granted Patent: US 7,039,149 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

The present invention comprises a phase-locked loop which generates a first clock signal, and a phase-locked loop which generates a second clock signal. An upper limit value of a jitter transmission frequency in the phase-locked loop in which a jitter signal is transmitted to the first clock signal without being suppressed, is not less than an upper limit value of a jitter transmission frequency. An upper limit value of a jitter transmission frequency from the phase-locked loop to the phase-locked loop in which a jitter signal is transmitted to the second clock signal without being suppressed, is not more than an upper limit value of a jitter transmission frequency.

Claims

1. A data clock regenerating apparatus comprising:

a first phase-locked loop which generates a first clock signal that is synchronous with a frequency of an input data signal and that is also in phase synchronism with a change point of the data signal;

a first discriminating unit which regenerates the input data signal by discriminating this input data signal with the first clock signal;

a second phase-locked loop which generates a second clock signal of which frequency and phase are synchronous with the first clock signal; and

a second discriminating unit that regenerates an output data signal of the first discriminating unit by discriminating this output data signal with the second clock signal, wherein

an upper limit value of a jitter transmission frequency in the first phase-locked loop in which a jitter signal superimposed on the input data signal is transmitted to the first clock signal without being suppressed, is not less than an upper limit value of a jitter transmission frequency that is required in the apparatus, and

an upper limit value of a jitter transmission frequency from the first phase-locked loop to the second phase-locked loop in which a jitter signal superimposed on the input data signal is transmitted to the second clock signal without being suppressed, is not more than an upper limit value of a jitter transmission frequency that is required in the apparatus.

2. The data clock regenerating apparatus according to claim 1, further comprising a frequency-dividing unit which divides the first clock signal generated by the first phase-locked loop, thereby to generate a plurality of parallel low-speed clock signals, and outputs the generated parallel low-speed clock signals to the second phase-locked loop as a reference clock, wherein

the first discriminating unit discriminates the input data signal according to the low-speed clock signal that is output from the frequency-dividing unit.

3. The data clock regenerating apparatus according to claim 1, further comprising a frequency-dividing unit which divides the first clock signal generated by the first phase-locked loop, thereby to generate a plurality of parallel low-speed clock signals, and outputs the generated parallel low-speed clock signals to the second phase-locked loop as a reference clock, wherein

the first discriminating unit discriminates the input data signal according to the first clock signal generated by the first phase-locked loop input as a differential signal, and outputs two series of parallel low-speed data signals.

4. The data clock regenerating apparatus according to claim 1, further comprising:

a frequency-dividing unit which divides the first clock signal generated by the first phase-locked loop, thereby to generate a plurality of parallel low-speed clock signals, and outputs the generated parallel low-speed clock signals to the second phase-locked loop as a reference clock; and

a third discriminating unit which discriminates a data signal output from the first discriminating unit according to the low-speed clock signal that is output from the frequency-dividing unit, and outputs this data signal to the second discriminating unit.

5. The data clock regenerating apparatus according to claim 4, wherein

the first discriminating unit discriminates the input data signal according to the low-speed clock signal that is output from the frequency-dividing unit.

6. The data clock regenerating apparatus according to claim 1, wherein the second discriminating unit comprises:

a frequency-dividing unit which divides the second clock signal generated by the second phase-locked loop, thereby to generate a plurality of parallel low-speed clock signals; and

a data-dividing unit which discriminates a data signal output from the first discriminating unit according to the plurality of parallel low-speed clock signals, and expands this data signal into a parallel low-speed data.