Low overhead exception checking

• US 20030093456A1
• Filed: 10/22/2002
• Published: 05/15/2003
• Est. Priority Date: 10/25/2001
• Status: Abandoned Application

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Lindwer, Menno Menasshe, Steinbusch, Otto Lodewijk
• Application Number:
  US10/277,538
• Publication Number:
  US 20030093456A1
• Time in Patent Office: Days
• US Class Current: 718/1
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053

Abstract

Exception detection is expedited in virtual machine interpreter (VMI) accelerator hardware (120) by dispatching fetched bytecodes along with instructions that cause a processor interrupt if the fetched bytecodes cause an exception to be thrown. The processor interrupt serves to indicate to the VMI (120) that an exception condition exists, thereby obviating the need to for the VMI (120) to wait for the result of an exception check to be sent from the CPU (110) to the VMI (120).

Claims

1. A method of processing virtual machine instructions, comprising:

fetching a virtual machine instruction;

processing the virtual machine instruction into native instructions executable by a processor;

dispatching the processed native instructions to the processor for execution along with native instructions that cause a processor interrupt if execution of the processed native instructions results in an illegal operation;

executing the processed native instructions and the native instructions that cause a processor interrupt if execution of the processed native instructions results in an illegal operation.

2. The method of claim 1, wherein fetching and processing the virtual machine instruction into native instructions executable by a processor is accomplished by a Virtual Machine Interpreter (VMI) virtual machine hardware accelerator.

3. The method of claim 1, further comprising generating native instructions that cause a processor interrupt if execution of the processed native instructions results in an illegal operation.

4. The method of claim 3, wherein executing the processed native instructions and the native instructions that cause a processor interrupt if execution of the processed native instructions results in an illegal operation further comprises:

generating an exception check result if execution of the dispatched native instructions results in an illegal operation; and

executing the native instructions that cause a processor interrupt if execution of the processed native instructions results in an illegal operation by performing an algorithm on the exception check result where a processor interrupt is caused.

5. An apparatus (100) for processing virtual machine instructions, comprising:

a processor (110) having a native instruction set and configured to execute native instructions;

an instruction memory (150), configured to store virtual machine instructions; and

a preprocessor (120), configured to fetch virtual machine instructions from the instruction memory, to process the fetched virtual machine instructions into native instructions executable by the processor, to append native instructions that cause a processor interrupt if execution of the processed virtual machine instructions result in an illegal operation, and to dispatch the processed native instructions and the appended native instruction to the processor for execution.

6. The apparatus (100) of claim 5, wherein the preprocessor (120) is a Virtual Machine Interpreter (VMI) virtual machine hardware accelerator.

7. The apparatus (100) of claim 5, wherein the preprocessor (120) is further configured to generate the native instructions that cause a processor interrupt if execution of the processed native instructions results in an illegal operation.

8. The apparatus (100) of claim 7, wherein the processor (110) is further configured to execute the processed native instructions and the appended native instructions, to generate an exception indicator if execution of the dispatched native instructions results in an illegal operation, and to execute the appended native instructions by performing an algorithm on the exception indicator that causes a processor interrupt.