Computer arrangement using non-refreshed dram

• US 20030093615A1
• Filed: 10/09/2002
• Published: 05/15/2003
• Est. Priority Date: 12/06/1999
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: De Jong, Eduard Karel
• Granted Patent: US 7,020,740 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4078 Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells protection of memory contents during checking or testing G11C29/52

Abstract

A computer arrangement with a processor (5) and at least one memory unit (7, 9, 11, 13) connected to the processor (5) and including dynamic random access memory (13), wherein the computer arrangment is arranged to use but not to refresh at least part of the dynamic random access memory (13) while running a program.

Claims

1. A computer arrangement comprising a processor (5) and at least one memory unit (7, 9, 11, 13) connected to said processor (5) and comprising dynamic random access memory (13) having a predetermined retention time, said computer arrangement being arranged for running a predetermined program on said processor (5) while temporarily storing data during a storage time in at least part of said dynamic random access memory (13), wherein said storage time is shorter than said retention time and said computer arrangement is arranged to use but not to refresh said at least part of said dynamic random access memory (13) comprising said data during said running of said program.

2. A computer arrangement according to claim 1, wherein said at least part of said dynamic random access memory (13) is not connected to refresh circuitry.

3. A computer arrangement according to claim 1 or 2, wherein said dynamic random access memory is divided into two or more memory banks (13(1), 13(2), 13(3), 13(4)), each memory bank being independently accessible for storing or retrieving of data.

4. A computer arrangement according to claims 1, 2 or 3, wherein a further part (13(1)) of said dynamic random access memory is controlled by additional logic circuitry (15).

5. A computer arrangement according to claim 4, wherein said additional logic circuitry (15) is connected to a communication interface (3).

6. A computer arrangement according to claim 4, comprising an additional computing unit (17) connected to said additional logic circuitry (15).

7. A computer arrangement according to any of the preceding claims, wherein said dynamic random access memory is provided with a plurality of word lines, each word line comprising an array of memory cells, at least one of said word lines comprising a series of one or more memory cells connected to checking logic circuitry (19) connected to said processor (5) and arranged to carry out the following steps:

(a) writing predetermined logic values into said series of one or more memory cells whenever the processor writes data into said at least one word line;

(b) reading actual content of said series of one or more memory cells whenever said at least one word line is read by said processor;

(c) checking whether said actual content equals said predetermined logic values;

(d) transmitting a warning signal to said processor upon detecting that said actual content does not equal said predetermined values.

8. A computer arrangement according to claim 7, wherein said series of one or more memory cells of said at least one word line is implemented using memory cells with less memory retention time than the other memory cells in said at least one word line.

9. A computer arrangement according to one of the preceding claims, implemented as single chip arrangement.

10. A smart card (1) provided with a computer arrangement according to one of the preceding claims.

11. A terminal (2) provided with a terminal processor (6) and a terminal communication interface (4) connected to said terminal processor (6) and arranged for communicating with a computer arrangement comprising a processor (5), a communication interface (3) and at least one memory unit (7, 9, 11, 13), said communication interface (3) and said at least one memory unit (7, 9, 11, 13) being connected to said processor (5), said at least one memory unit comprising memory (7;

9;

11) for storing a computer program with a predetermined sequence of instructions and dynamic random access memory (13), said computer arrangement being arranged to use but not to refresh at least part of said dynamic random access memory (13) while running said program, wherein said terminal processor (6) is arranged to carry out the following steps;

(a) emulating said computer program;

(b) analyzing time period necessary for the processor (5) of the computer arrangement (1) to carry out each instruction of said sequence of instructions and determining all retention times necessary for the processor (5) to temporarily store data in said at least part of said dynamic random access memory (13) during carrying said sequence of instructions;

(c) establishing sets of consecutive instructions for which said retention times are longer than a predetermined refresh time;

(d) adding additional instructions to said sets of consecutive instructions in order to obtain modified retention times for those sets of consecutive instructions which modified retention times are shorter than said predetermined refresh times.

12. A method of running a program on a computer arrangement comprising a processor (5) and at least one memory unit (7, 9, 11, 13) connected to said processor (5) and comprising dynamic random access memory (13) having a predetermined retention time, the method comprising the step of running a predetermined program on said processor (5) while temporarily storing data during a storage time in at least part of said dynamic random access memory (13), wherein said storage time is shorter than said retention time and said method further comprises the step of using but not refreshing said at least part of said dynamic random access memory (13) comprising said data during said running of said program.

13. A computer program comprising instructions executable on a computer arrangement comprising a processor (5) and at least one memory unit (7, 9, 11, 13) connected to said processor (5) and comprising dynamic random access memory (13) having a predetermined retention time, the computer program while running on said computer arrangement comprising the step of temporarily storing data during a storage time in at least part of said dynamic random access memory (13), wherein said storage time is shorter than said retention time and said computer program further comprises the step of using but not refreshing said at least part of said dynamic random access memory (13) comprising said data during said running of said program.

14. A computer readable medium comprising a computer program as claimed in claim 13.