System on a chip with multiple power planes and associate power management methods
First Claim
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1. A system on a chip comprising:
- a first power plane for powering a core logic portion of the system on a chip;
a second power plane for powering selected analog circuitry of the system on a chip;
clock generation circuitry for generating clocks for clocking operations of selected circuits of the system on the chip in response to a signal generated by an oscillator; and
power control circuitry operable to;
in a first mode, switch-off power to the first and second power planes, the oscillator being enabled; and
in a second mode, disable the clock generation circuitry and switch power to the first and second power planes, the oscillator being enabled.
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Abstract
A system-on-a-chip includes a first and second power planes for respectively powering core logic and analog portions of the system. Clock generation circuitry is included for generating clocks for clocking operations of selected circuits of the system on a chip in response to a signal generated by an oscillator. Power control circuitry switches off power to the first and second power planes in a first mode, with the oscillator being enabled. In a second mode, the power control circuitry disables the clock generation circuitry and switches power to the first and second power planes, the oscillator being enabled.
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Citations
20 Claims
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1. A system on a chip comprising:
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a first power plane for powering a core logic portion of the system on a chip;
a second power plane for powering selected analog circuitry of the system on a chip;
clock generation circuitry for generating clocks for clocking operations of selected circuits of the system on the chip in response to a signal generated by an oscillator; and
power control circuitry operable to;
in a first mode, switch-off power to the first and second power planes, the oscillator being enabled; and
in a second mode, disable the clock generation circuitry and switch power to the first and second power planes, the oscillator being enabled. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of power control in a system on a chip including core logic powered by a first power plane, analog circuitry powered by a second power plane and clock generation circuitry for generating clocks for operating selected circuitry of the core logic in response to a clock signal generated by an oscillator comprising the steps of:
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during a normal mode of operation, selectively powering the first and second power planes and running the oscillator;
during a super stand-by mode, selectively terminating power to the first and second power planes and running the oscillator; and
during a stand-by mode, selectively powering the first and second power planes, disabling the clock generation circuitry and running the oscillator. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A system on a chip comprising:
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a microprocessor operating from a first bus and operating in response to a microprocessor clock;
a digital signal processor operating from the first bus and operating in response to a DSP clock;
a first power plane for providing power to said microprocessor and said digital signal processor;
analog circuitry operating from a second bus coupled to the first bus by a bridge;
a second power plane for providing power to said analog circuitry; and
power control circuitry operable in a first stand-by mode decouple power from said first and second power planes and in a second stand-by mode to terminate generation said microprocessor and DSP clocks while maintaining power to said first and second power planes. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification