Sub-Micron high input voltage tolerant input output (I/O) circuit
First Claim
1. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
- an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage, coupled to the gate of the second upper MOS device, the third bias voltage comprising a fixed voltage when VPAD is less than the VDDO voltage and comprising a voltage equal to VPAD otherwise; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device, the fourth bias voltage comprising a first fixed voltage when VPAD is less than a pre-determined value and comprising a voltage higher than the first fixed voltage otherwise.
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Accused Products
Abstract
A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.
46 Citations
41 Claims
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1. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage, coupled to the gate of the second upper MOS device, the third bias voltage comprising a fixed voltage when VPAD is less than the VDDO voltage and comprising a voltage equal to VPAD otherwise; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device, the fourth bias voltage comprising a first fixed voltage when VPAD is less than a pre-determined value and comprising a voltage higher than the first fixed voltage otherwise. - View Dependent Claims (2, 3, 5)
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4. An apparatus for providing a well biasing voltage the apparatus comprising:
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a supply voltage VDDO input for accepting a supply voltage;
a VPAD input for accepting the voltage on an I/O pad; and
a bias output for providing a bias voltage equal to VDDO when VPAD is less than VDDO and for providing VPAD otherwise.
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6. An apparatus that generates a bias voltage (Bias_Mid ) the apparatus comprising:
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an input that accepts an input/output circuit pad voltage (Vpad);
an input that accepts an output enable signal;
an input that accepts a first input voltage VDDO;
an input that accepts a first input voltage VDDP;
an output circuit that, if the output enable signal is at an enable value, provides VDDP voltage to Bias_Mid and provides an output that depends on the pad voltage otherwise. - View Dependent Claims (7, 8)
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9. An apparatus for biasing a device well the apparatus comprising:
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a first circuit that accepts an input/output pad voltage Vpad;
a second circuit that compares Vpad to a comparison voltage; and
a third circuit that couples the device well to be biased to a first bias voltage if the pad voltage is less than the first bias voltage and to Vpad otherwise. - View Dependent Claims (10)
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11. An apparatus for generating a bias voltage (VGP1) the apparatus comprising:
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an input that accepts a pad voltage;
an input that accepts a Bias—
1 voltage, the bias voltage being at one level if the output is enabled and being at a higher voltage if the output is disabled;
and a circuit that-provides a lower voltage VDDC as a VGP1 if the pad voltage is less than VDDO and provides the pad voltage as VGP1 otherwise.
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12. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage, coupled to the gate of the second upper MOS device; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device, the fourth bias voltage being in a range, the range having a maximum value of VDDP+VT and a minimum value of (VDDO−
VTp), where VDDP and VDDO are power supply voltages and VT and VTp are offset voltages;
- View Dependent Claims (13, 14)
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15. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device depending on the voltage on the I/O pad (VPAD), said fourth bias voltage being restricted to a range between a predetermined maximum value and a predetermined minimum value.
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16. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device depending on the voltage on the I/O pad (VPAD), the fourth bias voltage being restricted to a range having a maximum value of (VDDP−
VT) and a minimum value of (VDDO−
VTp), where VDDP and VDDO are power supply voltages and VT and VTp are offset voltages. - View Dependent Claims (17, 18)
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19. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device depending on the voltage on the I/O pad (VPAD) when the pad is in an output disable mode, and said bias circuit providing a fixed fourth bias voltage to the gate of the first lower MOS device when the pad is in an output enable mode. - View Dependent Claims (20)
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21. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device equal to the voltage on the I/O pad (VPAD) when the pad is in an output disable mode, and where the third bias voltage to the gate of the second upper MOS device equal to a fixed voltage when the pad is in an output enabled mode; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device. - View Dependent Claims (22)
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23. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device depending on the voltage on the I/O pad (VPAD), the fourth bias voltage being fixed to a lower voltage when the pad voltage is less than a predetermined value, and the fourth bias voltage being at a higher voltage when the pad voltage is higher than a predetermined value. - View Dependent Claims (24, 25, 26)
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27. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device said fourth bias restricted between a maximum and a minimum value when the pad is in an output disable mode, and said fourth bias voltage is a fixed voltage when the pad is in an output enable mode. - View Dependent Claims (28, 29, 30)
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31. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device depending on the voltage on the I/O pad (VPAD), said fourth bias circuit comprising a capacitive voltage divider. - View Dependent Claims (32)
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33. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device, wherein the fourth bias voltage is a fixed voltage when the I/O pad is an output enabled mode, and wherein the bias voltage is a capacitively divided portion of the pad voltage when the I/O pad is an output disabled mode. - View Dependent Claims (34)
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35. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device depending on the voltage on the I/O pad (VPAD) said third bias circuit comprising a capacitive voltage divider; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device. - View Dependent Claims (36)
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37. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO)and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device, wherein. the third bias voltage is a capacitively divided portion of the pad voltage when the pad voltage is less than a predetermined value and the third bias voltage is equal to the pad voltage when the pad voltage is greater than a predetermined value; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device. - View Dependent Claims (38)
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39. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
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an input/output (I/O) pad;
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO)and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;
a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;
a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the pad is in an output mode and VDDO voltage otherwise;
a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;
a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device, wherein the third bias voltage is a fixed voltage when the I/O pad is in the output enabled mode and where the third bias voltage is a capacitively divided portion of the I/O pad voltage when the I/O pad is in the output disabled mode and the I/O pad voltage is less than a predetermined value, and where the third bias voltage is equal to the I/O pad voltage when the I/O pad is in the output disabled mode and the I/O pad voltage is greater than a predetermined value; and
a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device. - View Dependent Claims (40, 41)
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Specification