Electronic array having nodes and methods

• US 20030094992A1
• Filed: 10/15/2002
• Published: 05/22/2003
• Est. Priority Date: 01/06/1999
• Status: Active Grant

• Current Assignee: Victorian Systems Incorporated
• Original Assignee: Victorian Systems Incorporated
• Inventors: Geysen, H. Mario
• Granted Patent: US 6,744,299 B2
• Time in Patent Office: Days
• US Class Current: 327/403
• CPC Class Codes: G05F 3/222 with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: G05F 3/265 using bipolar transistors only
• CPC Class Codes: G06N 3/065 Analogue means

Abstract

An electronic network comprises a plurality of nodes that each comprise a current input and a current output, and at least one transistor arranged as a first current mirror and a second current mirror. The first and the second current minors are complementary to each other such that an output of the first current mirror is operably connected to an input of the second current mirror. Resistive connections connect the nodes such that the output of one or more of the nodes is operably connected to the input of one or more of the nodes.

Claims

1. An electronic network comprising:

a plurality of nodes that are operably interconnected, wherein each node comprises a current input and a current output, and wherein each node further comprises at a first current mirror and a second current mirror, with the first and the second current mirrors being complementary to each other such that an output of the first current mirror is operably connected to an input of the second current mirror, and wherein the first and second current mirrors are selected from a group consisting of field effect transistors and bipolar transistors; and

wherein the nodes are connected such that the output of one or more of the nodes is operably connected to the input of one or more of the nodes.

2. A network as in claim 1, wherein at least some of the nodes further comprise a Schmitt trigger, an inverter and a capacitor.

3. A network as in claim 1, wherein the resistance between the current inputs and the current outputs of the nodes is in the range from about 0.001 ohm to about 1,000 mega ohms.

4. A network as in claim 1, wherein the first current mirror comprises a PNP bipolar transistor and the second current mirror comprises a NPN bipolar transistor.

5. A network as in claim 1, wherein the first current mirror comprises a P type field effect transistor and the second current mirror comprises a N type CMOS transistor.

6. A network as in claim 1, further comprising circuitry configured to provide an input current to at least one of the nodes.

7. A network as in claim 1, further comprising circuitry configured to convert a current output from at least one of the nodes to a different form of signal.

8. A network as in claim 1, further comprising a circuit element positioned between the output of the first current mirror and the input of the second current mirror.

9. A network as in claim 1, wherein the circuit element is selected from a group consisting of transistors and resistors.

10. A node for an electronic network, comprising:

a current input and a current output that are each configured to be operably coupled to a similar node in an electronic network;

a first current mirror and a second current mirror, with the first and the second current mirrors being complementary to each other such that an output of the first current mirror is connected to an input of the second current mirror, and wherein the first and second current mirrors are selected from a group consisting of field effect transistors and bipolar transistors.

11. A node as in claim 10, wherein the first current mirror comprises a PNP bipolar transistor and the second current mirror comprises a NPN bipolar transistor, a Schmitt trigger, an inverter and a capacitor.

12. A node as in claim 10, wherein the first current mirror comprises a P type field effect transistor and the second current mirror comprises a N type field effect transistor, a Schmitt trigger, an inverter and a capacitor.

13. A node as in claim 10, further comprising a circuit element positioned between the output of the first current mirror and the input of the second current mirror.

14. A network as in claim 13, wherein the circuit element is selected from a group consisting of transistors and resistors.

15. A method for processing current signals, the method comprising:

inputting one or more current signals into a current network, the network comprising a plurality of nodes, wherein each node comprises a current input and a current output, and wherein each node further comprises at least a first current mirror and a second current mirror, with the first and the second current mirrors being complementary to each other such that an output of the first current mirror is connected to an input of the second current mirror, and connections connecting the nodes such that the output of one or more of the nodes is operably connected to the input of one or more of the nodes, and wherein the first and second current mirrors are selected from a group consisting of field effect transistors and bipolar transistors;

permitting the current signal to pass through at least some of the nodes;

outputting one or more current signals from the network after passing through at least some of the nodes.

16. A method as in claim 15, further comprising varying at least some of the resistive connections to provide an arrangement of non-symmetric resistive connections in the network.

17. A method as in claim 16, wherein the varying step comprises spacing at least some of the nodes at different distances relative to each other or altering the connections of the current outputs of at least some of the nodes with the current inputs of at least some of the nodes with a controllable switch matrix.

18. A method as in claim 15, further comprising varying the speed of at least one of the nodes using a capacitor.

19. A method as in claim 15, further comprising supplying a certain voltage to at least some of the nodes.

20. A method as in claim 15, further comprising producing pulsed current signals to at least some of the nodes.

21. A method as in claim 15, further comprising positioning a circuit element between the output of the first current mirror and the input of the second current mirror.

22. A method as in claim 21, wherein the circuit element is selected from a group consisting of transistors and resistors.