Wide common mode differential input amplifier and method

• US 20030095003A1
• Filed: 03/20/2002
• Published: 05/22/2003
• Est. Priority Date: 11/19/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Li, Ning, Shieh, Jiann-Chyi Sam
• Granted Patent: US 6,788,142 B2
• Time in Patent Office: Days
• US Class Current: 330/253
• CPC Class Codes: H03F 3/45219 Folded cascode stages
• CPC Class Codes: H03F 3/45237 Complementary long tailed pairs having parallel inputs and being supplied in series
• CPC Class Codes: H03F 3/45632 in differential amplifiers with FET transistors as the active amplifying circuit H03F3/4578 takes precedence

Abstract

A wide input range amplifier includes a first and second stage. The first stage has first and second inputs, first and second outputs, and first, second and third voltage sources. The first stage accepts input signals having a first common mode voltage range and outputs a first output signal having a second common mode voltage range and being amplified a first amount. The second stage has first and second inputs connected to the first and second outputs of the first stage, respectively. The second stage accepts input signals having a common mode voltage in the second range and outputs a second output signal having a third common mode voltage range and being amplified a second amount.

Claims

1. A wide input range amplifier comprising:

a first stage having first and second inputs, first and second outputs, and first, second and third voltage sources, said first stage accepting input signals having a first common mode voltage range and outputting a first output signal having a second common mode voltage range and being amplified a first amount;

a second stage having first and second inputs connected to said first and second outputs of said first stage, respectively, said second stage accepting input signals having a common mode voltage in said second range and outputting a second output signal having a third common mode voltage range and being amplified a second amount.

2. The wide input range amplifier as recited in claim 1, wherein:

said first stage includes differential resistors loaded across said first and second outputs of said first stage, as a load of said first stage.

3. The wide input range amplifier as recited in claim 2, wherein said first stage includes two input stages, said two input stages including a first inputs stage of a first conductive type and a second input stage of a second conductive type.

4. The wide input range amplifier as recited in claim 1, wherein said second stage comprises a differential amplifier.

5. The wide input range amplifier as recited in claim 1, wherein said second stage comprises a current mode logic differential amplifier.

6. The wide input range amplifier as recited in claim 1, wherein said second stage includes a common source differential amplifier.

7. The wide input range amplifier as recited in claim 3, wherein said first input stage comprises complementary input stages.

8. The wide input range amplifier as recited in claim 7, wherein said complementary input stages comprise a first input stage of a first semi-conductor type, and a second input stage of a second semi-conductor type.

9. The wide input range amplifier as recited in claim 8, wherein said first input stage comprises a P-type coupled pair biased with a first current source, and said second input stage comprises an N-type coupled pair biased with a second current source.

10. The wide input range amplifier as recited in claim 1, wherein said first stage comprises a P-type common source pair connected to a first current source and an N-type common source pair connected to a second current source, and first and second differential resistors, and wherein

said first current source is connected to said first voltage source, said second current source is connected to said second voltage source, a gate of a first transistor of said P-type common source pair being connected to said first input, a gate of a second transistor of said P-type common source pair being connected to said second input, a gate of a first transistor of said N-type common source pair being connected to said first input, a gate of a second transistor of said N-type common source pair being connected to said second input, a drain of said first transistor of said P-type common source pair being connected to said first output, a drain of said second transistor of said P-type common source pair being connected to said second output, a drain of said first transistor of said N-type common source pair being connected to said first output, a drain of said second transistor of said N-type common source pair being connected to said second input, and said pair of load resistors being connected two each other and two said first and second outputs, and said mid-point of said pair of load resistors being connected to said third voltage source.

11. The wide input range amplifier as recited in claim 10, wherein said third voltage source supplies approximately half of a voltage of said first voltage source, and said second voltage source is ground.

12. The wide input range amplifier as recited in claim 1, wherein said first stage further comprises complementary first and second input pairs, first and second differential resistors, and a first and second pair of cascoded transistors, and wherein

said first input pair is of a first semi-conductor type and said second input pair is of a second semi-conductor type, and said load resistors are loaded across said first and second outputs as load resistors.

13. The wide input range amplifier as recited in claim 12, wherein said first input pair is biased by a first current source, said second input pair is biased by a second current source, a first and second transistor of said first cascoded pair is biased by a third and fourth current source respectively, a first and second transistor of said second cascoded pair is biased by a fifth and sixth current source respectively, said first cascoded pair is cascoded to an output of said second input pair, and said second cascoded pair is cascoded to an output of said first input pair.

14. The wide input range amplifier as recited in claim 13, wherein a drain of a first transistor of said first input pair is connected to a source of a first transistor of said second cascoded pair, a drain of a second transistor of said first input pair is connected to a source of a second transistor of said second cascoded pair, a drain of a first transistor of said second input pair is connected to a source of a second transistor of said first cascoded pair, and a drain of a second transistor of said second input pair is connected to a source of a second transistor of said first cascoded pair.

15. The wide input range amplifier as recited in claim 11, wherein said first voltage source has a voltage approximately twice that of said third voltage source, and said second voltage source is ground.

16. The wide input range amplifier as recited in claim 10, wherein said first and second differential resistors comprise active load transistors.

17. The wide input range amplifier as recited in claim 12, wherein said first and second differential resistors comprise active load transistors.

18. The wide input range amplifier as recited in claim 13, wherein said third and fourth current sources each comprise a transistor of a first semi-conductor type connected to said first voltage source, and said third and fourth current sources each comprise a transistor of a second semi-conductor type connected to said second voltage source.

19. The wide input range amplifier as recited in claim 13, further comprising a first, second, third and fourth bias voltage, said first bias voltage biasing said first, third and fourth current sources, said second bias voltage biasing said first cascoded pair, aid third bias voltage biasing said second cascoded pair, and said fourth bias voltage biasing said second, fifth and sixth current sources.

20. A method of buffering an input signal, said method comprising:

providing a first amplifier stage for receiving an input signal having a first voltage range, amplifying said input signal a first amount, and outputting an output signal having a second voltage range being amplified said first amount;

providing a second amplifier stage for receiving said output signal from said first amplifier stage, amplifying said output signal a second amount, and outputting a differential output signal having a third voltage range being amplified said second amount.

21. The method as recited in claim 20, wherein said providing a first amplifier stage step comprises:

providing complementary input pairs for receiving said input signal,

configuring a first input pair of said complementary input pairs to be OFF and a second input pair of said complementary input pairs to be ON, when said input signal is above a first input voltage, and

configuring said first input pair of said complementary input pairs to be ON and said second input pair of said complementary input pairs to be OFF, when said input signal is below a first input voltage.

22. The method as recited in claim 20, wherein said providing a first amplifier stage step comprises:

providing first and second differential resistors as a load across the output of said first amplifier stage.

23. The method as recited in claim 21, wherein said providing a first amplifier stage step further comprises:

providing a first cascoded pair between the output of said first amplifier stage and cascoded with an output of said second input pair, and

providing a second cascoded pair between the output of said first amplifier stage and cascoded with an output of said first input pair.

24. The method as recited in claim 21, wherein said providing complementary input pairs step comprises:

providing said first input pair being a first semi-conductor type, and

providing said second input pair being a second semi-conductor type.

25. The method as recited in claim 20, wherein said providing a second amplifier stage step comprises providing a differential amplifier for receiving said output signal from said first amplifier stage.

26. The method as recited in claim 20, wherein said providing a second amplifier stage step comprises providing a current mode logic differential amplifier for receiving said output signal from said first amplifier stage.

27. The method as recited in claim 20, wherein said providing a second amplifier stage step comprises providing a common source differential amplifier for receiving said output signal from said first amplifier stage.

28. The method as recited in claim 20, wherein said providing a first amplifier stage step further comprises:

providing a P-type common source pair connected to a first current source and an N-type common source pair connected to a second current source, and first and second differential resistors,

loading said first and second differential resistors across said output of said first stage amplifier,

connecting said first current source to a first voltage source,

connecting said second current source to a second voltage source,

connecting a gate of a first transistor of said P-type common source pair to said first input,

connecting a gate of a second transistor of said P-type common source pair to said second input,

connecting a gate of a first transistor of said N-type common source pair to said first input,

connecting a gate of a second transistor of said N-type common source pair to said second input,

connecting a drain of said first transistor of said P-type common source pair to said first output,

connecting a drain of said second transistor of said P-type common source pair to said second output,

connecting a drain of said first transistor of said N-type common source pair to said first output,

connecting a drain of said second transistor of said N-type common source pair to said second input,

connecting said first and second differential resistors to each other and to said first and second outputs, and

connecting a mid-point of said first and second differential resistors to a third voltage source.

29. The method as recited in claim 28, wherein said providing a first amplifier stage step further comprises setting said third voltage source to a voltage approximately half of that of said first voltage source, and

setting said second voltage source to ground.

30. The method as recited in claim 20, wherein said providing a first amplifier stage step further comprises:

providing complementary first and second input pairs, said first input pair is of a first semi-conductor type and said second input pair is of a second semi-conductor type,

providing first and second differential resistors connected across said output of said first amplifier stage as load resistors, and

providing a first and second pair of cascoded transistors, said first pair of cascoded transistors cascoded with said second input pair, and said second pair of cascoded transistor cascoded with said first input pair.

31. The method as recited in claim 30, wherein said providing a first amplifier stage step further comprises:

biasing said first input pair with a first current source,

biasing said second input pair with a second current source,

biasing a first and second transistor of said first cascoded pair with a third and fourth current source respectively, and

biasing a first and second transistor of said second cascoded pair with a fifth and sixth current source respectively.

32. The method as recited in claim 31, wherein said providing a first amplifier stage step further comprises:

connecting a drain of a first transistor of said first input pair to a source of a first transistor of said second cascoded pair,

connecting a drain of a second transistor of said first input pair to a source of a second transistor of said second cascoded pair,

connecting a drain of a first transistor of said second input pair to a source of a second transistor of said first cascoded pair, and

connecting a drain of a second transistor of said second input pair to a source of a second transistor of said first cascoded pair.

33. The method as recited in claim 30, wherein said providing a first amplifier stage step further comprises:

providing said first voltage source having a voltage approximately twice that of said third voltage source, and said second voltage source is ground.

34. The method as recited in claim 30, wherein said providing a first amplifier stage step further comprises:

providing active load transistors as said first and second differential resistors.

35. The method as recited in claim 28, wherein said providing a first amplifier stage step further comprises:

providing active load transistors as said first and second differential resistors.

36. A method for receiving a signal, said method comprising the steps of:

receiving a thick device signal having a first common mode range;

amplifying said thick device signal a first amount and stepping said thick device signal down to a first thin device signal having a second common mode range; and

amplifying said thin device signal a second amount and outputting a second thin device signal having a third common mode voltage range.

37. The method as recited in claim 36, wherein said step of amplifying said thick device signal includes steps of:

determining whether said first common mode range is above or below a threshold voltage, and

amplifying said thick device signal a first amount and stepping said thick device signal down to said first thin device signal based on the determination.

38. The method as recited in claim 36, wherein said step of amplifying said thin device signal includes a step of folding gain of said thin device signal to differential transistors to produce said second thin device signal as a differential output.

39. The method a s recited in claim 38, further comprising a step of outputting said differential output to a core digital system.

40. The method as recited in claim 37, wherein said steps of determining whether said first common mode range is above or below a threshold voltage, and said step of amplifying said thick device signal include using complementary input pairs, a first pair of said complementary input pairs performing said step of amplifying said thick device signal when said first common mode range is above said threshold voltage, and a second pair of said complementary input pairs performing said step of amplifying said thick device signal when said first common mode range is below said threshold voltage.

41. The method as recited in claim 38, wherein said step of folding gain of said thin device signal to differential transistors includes using at least one cascoded amplifier to perform said step of folding.

42. A wide input range amplifier comprising:

a first amplifying means for accepting input signals having a first common mode voltage range and outputting a first output signal having a second common mode voltage range and being amplified a first amount;

a second amplifying means for accepting input signals having a common mode voltage in said second range and outputting a second output signal having a third common mode voltage range and being amplified a second amount.

43. The wide input range amplifier as recited in claim 42, wherein:

said first amplifying means includes a differential resistor means for providing a load of said first amplifying means.

44. The wide input range amplifier as recited in claim 43, wherein said first amplifying means includes a first input stage of a first conductive type and a second input stage of a second conductive type.

45. The wide input range amplifier as recited in claim 42, wherein said second amplifying means comprises a differential amplifying means for producing a differential signal.

46. The wide input range amplifier as recited in claim 42, wherein said second amplifying means comprises a current mode logic differential amplifying means for producing a differential signal for digital core logic.

47. The wide input range amplifier as recited in claim 42, wherein said second common mode voltage range approximate half said first common mode voltage range, and said third common mode voltage range is negligible.