Optical multiplexer

• US 20030095210A1
• Filed: 10/01/2001
• Published: 05/22/2003
• Est. Priority Date: 10/01/2001
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Huntley, Chris
• Granted Patent: US 7,133,401 B2
• Time in Patent Office: Days
• US Class Current: 348/705
• CPC Class Codes: H04N 5/268 Signal distribution or switching

Abstract

An optical multiplexer is provided that operates in a synchronous optical network (SONET). The multiplexer includes a plurality of inputs and a processor operationally coupled to the inputs. The multiplexer also includes a plurality of optical outputs coupled to the inputs via the processor, wherein the processor is configured to receive data from at least two of the plurality of inputs. The processor is also configured to packetize the received data and route the packetized data to at least two of the plurality of optical outputs.

Claims

1. A video optical multiplexer comprising:

a plurality of optical video inputs;

a processor operationally coupled to said optical video inputs; and

a plurality of optical video outputs coupled to said optical video inputs via said processor, said processor configured to;

receive video data from at least two of said plurality of optical video inputs;

packetize the received video data; and

route the packetized video data to at least two of said plurality of optical video outputs.

2. A multiplexer in accordance with claim 1 further comprising a Field Programmable Logic Gate Array (FPGA) operationally coupled to said processor, said FPGA configured to detect a start of field (SOF) data pattern for the packetized video data.

3. A multiplexer in accordance with claim 1 further comprising:

at least one optical audio input operationally coupled to said processor; and

at least one optical audio output operationally coupled to said processor, said processor further configured to packetized audio data received from said optical audio input in a packet of equal size to a packet size of said packetized video data.

4. A multiplexer in accordance with claim 3 wherein each said audio packet and each said video packet comprise between twenty bytes per packet and thirty bytes per packet.

5. A multiplexer in accordance with claim 4 wherein each said audio packet and each said video packet comprise approximately twenty-five bytes per packet.

6. A multiplexer in accordance with claim 4 wherein each said audio packet and each said video packet comprise twenty-five bytes per packet.

7. A multiplexer in accordance with claim 2 wherein said FPGA comprises a pacer circuit configured to pace an output of the routed packetized video data.

8. A multiplexer in accordance with claim 1 wherein said plurality of optical video inputs and said plurality of optical video outputs are connected in a linear topology.

9. A multiplexer in accordance with claim 7 wherein said pacer circuit configured to:

output the routed packetized video data at a first resolution when the packetized video data is interlaced; and

output the routed packetized video data at a second resolution when the packetized video data is non-interlaced.

10. A multiplexer in accordance with claim 7 wherein said pacer circuit configured to:

output the routed packetized video data at a first resolution when the packetized video data is interlaced; and

output the routed packetized video data at a second resolution when the packetized video data is non-interlaced, the second resolution approximately one-half the first resolution.

11. A multiplexer in accordance with claim 1 wherein said processor further configured to route each packetized video data package based upon a video network address (VNA) contained in each packet using a VNA lookup table.

12. A multiplexer in accordance with claim 1 wherein each said optical video input is configured to:

receive an analog video input from an analog video source; and

output to said processor an optical digital video signal.

13. A multiplexer in accordance with claim 1 wherein each optical video output is configured to:

receive from said processor an optical digital video signal; and

output an analog video signal.

14. A multiplexer in accordance with claim 1 wherein said plurality of optical video inputs and said plurality of optical video outputs are connected in a tree topology.

15. A multiplexer in accordance with claim 11 wherein each VNA comprises thirteen bits.

16. A method for operating a synchronous optical- network (SONET), said method comprising:

providing a plurality of optical video inputs;

operationally coupling a processor to the optical video inputs;

operationally coupling a plurality of optical video outputs to the optical video inputs via the processor;

configuring the processor to;

receive video data from at least two of the plurality of optical video inputs;

packetize the received video data; and

route the packetized video data to at least two of the plurality of optical video outputs.

17. A method in accordance with claim 16 further comprising:

operationally coupling a Field Programmable Logic Gate Array (FPGA) operationally coupled to the processor; and

configuring the FPGA to detect a start of field (SOF) data pattern for the packetized video data.

18. A method in accordance with claim 16 further comprising:

operationally coupling at least one optical audio input to the processor;

operationally coupling at least one optical audio output to the processor; and

configured the processor to packetized audio data received from the optical audio input in a packet of equal size to a packet size of the packetized video data.

19. A method in accordance with claim 18 wherein each audio packet and each video packet comprise between twenty bytes per packet and thirty bytes per packet.

20. A method in accordance with claim 19 wherein each audio packet and each video packet comprise approximately twenty-five bytes per packet.

21. A method in accordance with claim 20 wherein each audio packet and each video packet comprise twenty-five bytes per packet.

22. A method in accordance with claim 17 further comprising:

providing a pacer circuit in the FPGA; and

configuring the pacer circuit to pace an output of the routed packetized video data.

23. A method in accordance with claim 16 further comprising connecting the plurality of optical video inputs and the plurality of optical video outputs in a linear topology.

24. A method in accordance with claim 22 further comprising configuring the pacer circuit to:

output the routed packetized video data at a first resolution when the packetized video data is interlaced; and

output the routed packetized video data at a second resolution when the packetized video data is non-interlaced.

25. A method in accordance with claim 22 further comprising configuring the pacer circuit to:

output the routed packetized video data at a first resolution when the packetized video data is interlaced; and

output the routed packetized video data at a second resolution when the packetized video data is non-interlaced, wherein the second resolution is approximately one-half the first resolution.

26. A method in accordance with claim 16 further comprising configuring the processor to route each packetized video data package based upon a video network address (VNA) contained in each packet using a VNA lookup table.

27. A method in accordance with claim 16 further comprising configuring each optical video input to:

receive an analog video input from an analog video source; and

output to the processor an optical digital video signal.

28. A method in accordance with claim 16 further comprising configuring each optical video output to:

receive from the processor an optical digital video signal; and

output an analog video signal.

29. A method in accordance with claim 16 further comprising connecting the plurality of optical video inputs and the plurality of optical video outputs in a tree topology.

30. A method in accordance with claim 26 wherein each VNA comprises thirteen bits.

31. An optical system comprising:

a plurality of cameras;

a plurality of optical video inputs operationally coupled to said cameras;

a processor operationally coupled to said optical video inputs; and

a plurality of optical video outputs coupled to said optical video inputs via said processor, said optical video outputs also coupled to a plurality of video monitors, said processor configured to;

receive video data from at least two of said plurality of optical video inputs;

packetize the received video data; and

route the packetized video data to at least two of said plurality of optical video outputs.

32. A system in accordance with claim 31 further comprising a Field Programmable Logic Gate Array (FPGA) operationally coupled to said processor, said FPGA configured to detect a start of field (SOF) data pattern for the packetized video data.

33. A system in accordance with claim 31 further comprising:

at least one optical audio input operationally coupled to said processor; and

at least one optical audio output operationally coupled to said processor, said processor further configured to packetized audio data received from said optical audio input in a packet of equal size to a packet size of said packetized video data.

34. A system in accordance with claim 33 wherein each said audio packet and each said video packet comprise between twenty bytes per packet and thirty bytes per packet.

35. A system in accordance with claim 34 wherein each said audio packet and each said video packet comprise approximately twenty-five bytes per packet.

36. A system in accordance with claim 34 wherein each said audio packet and each said video packet comprise twenty-five bytes per packet.

37. A system in accordance with claim 32 wherein said FPGA comprises a pacer circuit configured to pace an output of the routed packetized video data.

38. A system in accordance with claim 31 wherein said plurality of optical video inputs and said plurality of optical video outputs are connected in a linear topology.

39. A system in accordance with claim 37 wherein said pacer circuit configured to:

output the routed packetized video data at a first resolution when the packetized video data is interlaced; and

output the routed packetized video data at a second resolution when the packetized video data is non-interlaced.

40. A system in accordance with claim 37 wherein said pacer circuit configured to:

output the routed packetized video data at a first resolution when the packetized video data is interlaced; and

output the routed packetized video data at a second resolution when the packetized video data is non-interlaced, the second resolution approximately one-half the first resolution.

41. A system in accordance with claim 31 wherein said processor further configured to route each packetized video data package based upon a video network address (VNA) contained in each packet using a VNA lookup table.

42. A system in accordance with claim 31 wherein each said optical video input is configured to:

receive an analog video input from an analog video source; and

output to said processor an optical digital video signal.

43. A system in accordance with claim 31 wherein each optical video output is configured to:

receive from said processor an optical digital video signal; and

output an analog video signal.

44. A system in accordance with claim 31 wherein said plurality of optical video inputs and said plurality of optical video outputs are connected in a tree topology.

45. A system in accordance with claim 41 wherein each VNA comprises thirteen bits.

46. A optical multiplexer comprising:

a plurality of inputs;

a processor operationally coupled to said inputs; and

a plurality of optical outputs coupled to said inputs via said processor, said processor configured to;

receive data from at least two of said plurality of inputs;

packetize the received data; and

route the packetized data to at least two of said plurality of optical outputs.

47. A multiplexer in accordance with claim 46 wherein said multiplexer is operating a synchronous optical network.

48. A multiplexer in accordance with claim 47 where said optical inputs operationally coupled to at least one of an analog source and a digital source.

49. A multiplexer in accordance with claim 47 wherein said optical inputs operationally coupled to at least one optical source.

50. A multiplexer in accordance with claim 47 wherein said inputs are configured to receive an analog input and convert the analog input to an optical signal and send the optical signal to said processor.

51. A multiplexer in accordance with claim 50 wherein said processor further configured to send the converted optical signal to said optical outputs which convert the optical signal to a non-optical signal.