Inrush current control method using a dual current limit power switch

• US 20030095368A1
• Filed: 10/28/2002
• Published: 05/22/2003
• Est. Priority Date: 11/20/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Daniels, David G., Alhoussami, Aiman, Fowler, Tom L.
• Granted Patent: US 6,947,272 B2
• Time in Patent Office: Days
• US Class Current: 361/93.9
• CPC Class Codes: H02H 9/001 limiting speed of change of electric quantities, e.g. soft switching on or off progressive control of electronic switches for eliminating interferences H03K17/16
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/166 Soft switching
• CPC Class Codes: H03K 17/302 in field-effect transistor switches

Abstract

A current limit circuit regulates the current flow through a power switch 90 by measuring the current through the switch 90 and comparing it to a reference voltage V_REF that represents the limit current. When the current through the power switch 90 is greater than the limit current, the current in the power switch 90 is pulled lower by a driver circuit 92 which controls the power switch 90. By using a current limit reference voltage that has two levels, the power switch 90 has two current limit thresholds. Using a comparator 94 to compare the input voltage of the power switch 90 to the output voltage of the power switch 90, an output signal is generated to control the current limit threshold. When the input voltage and output voltage has a large differential voltage, a lower current limit threshold voltage is selected. When the input voltage and output voltage has a small differential voltage, an upper limit threshold voltage is selected.

Claims

1. A circuit comprising:

a switch;

a first comparator coupled to the switch for comparing an input of the switch to an output of the switch;

a current limit reference circuit coupled to the first comparator for providing a current reference that has a first reference level when a ratio of the output to the input is less than a fixed ratio, and a second reference level when the ratio of the output voltage to the input voltage is greater than the fixed ratio;

a second comparator coupled to the current limit reference circuit for comparing the current reference to a current level in the switch; and

a driver circuit coupled between the second comparator and a control node of the switch.

2. The device of claim 1 wherein the switch is a transistor.

3. The device of claim 1 wherein the switch is an NMOS transistor.

4. The device of claim 1 wherein the current limit reference circuit comprises a decode/multiplexer with two reference voltage inputs and an output coupled to an input of the second comparator.

5. The device of claim 4 further comprising:

a logic gate having an output coupled to the decode/multiplexer; and

a delay circuit coupled between an output of the first comparator and an input of the logic gate.

6. The device of claim 5 wherein the logic gate is an OR gate.

7. The device of claim 1 wherein the first comparator has a first input coupled to the output of the switch and a second input coupled to the input of the switch through a resistor divider circuit.

8. The device of claim 7 wherein the resistor divider circuit comprises:

a first resistor coupled between the input of the switch and the second input of the first comparator; and

a second resistor coupled between the second input of the first comparator and a ground node.

9. A dual current limit power switch device comprising:

a power switch having an input node, an output node, and a control node;

a driver coupled to the control node;

a first comparator having an output coupled to the driver and a first input coupled to a current detection node at the input node of the power switch;

a current limit reference circuit having an output coupled to a second input of the first comparator, and having a first input coupled to a first reference voltage node and a second input coupled to a second reference voltage node; and

a second comparator having a first input coupled to the output node of the power switch and a second input coupled to the input node of the power switch through a resistor divider, wherein the current limit reference circuit selects between the first and second reference voltages in response to the second comparator.

10. The device of claim 9 further comprising:

a logic gate having an output coupled to the current limit reference circuit; and

a delay circuit coupled between an output of the second comparator and an input of the logic gate.

11. The device of claim 10 wherein the logic gate is an OR gate having a first input coupled to the delay circuit and a second input coupled to a ground node.

12. The device of claim 9 wherein the power switch is a transistor.

13. The device of claim 9 wherein the power switch is an NMOS transistor.

14. The device of claim 9 wherein the current limit reference circuit is a decode/multiplexer.

15. The device of claim 9 wherein the resistor divider comprises:

a first resistor coupled between the input node of the power switch and the second input of the second comparator; and

a second resistor coupled between the second input of the second comparator and a ground node.

16. A method for driving a power switch comprising:

comparing an input voltage to an output voltage of the power switch;

generating a current limit reference that has a first signal level when a ratio of the output voltage to the input voltage is less than a fixed ratio, and a second signal level when the ratio of the output voltage to the input voltage is greater than the fixed ratio;

comparing the current limit reference to a current level in the power switch; and

reducing the current level in the power switch when the current level is greater than the current limit reference.