Baseband controller in a wireless local area network

• US 20030096634A1
• Filed: 11/08/2001
• Published: 05/22/2003
• Est. Priority Date: 11/08/2001
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Lin, John
• Granted Patent: US 7,123,877 B2
• Time in Patent Office: Days
• US Class Current: 455/560
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04W 28/06 Optimizing the usage of the radio link, e.g. header compression, information sizing , discarding information system modifying transmission characteristic according to link quality by modifying frame length H04L1/0007; dynamic adaptation of the packet size for flow control or congestion control H04L47/365
• CPC Class Codes: H04W 28/14 using intermediate storage
• CPC Class Codes: H04W 84/12 WLAN [Wireless Local Area Networks]
• CPC Class Codes: H04W 84/18 Self-organising networks, e.g. ad-hoc networks or sensor networks

Abstract

A baseband controller includes a micro-sequencer that is formed to include special hardware resources and a configuration that facilitates using the micro-sequencer as a real-time baseband controller. The inventive micro-sequencer includes a 72-bit correlator that may also be used as an accumulator, wherein the topology includes the correlator being able to communicate with a 72-bit arithmetic logic unit which, therefore, enables the correlator to act as an accumulator, as well as a plurality of clocks and timers that facilitate the timing functionality that is required to satisfy Bluetooth specifications. More specifically, the micro-sequencer includes at least four clocks and eight timers in one embodiment of the present invention. The four clocks include an externally driven Bluetooth clock, an externally driven real-time clock, a native Bluetooth clock and a native real-time clock. The micro-sequencer of the described embodiment further includes at least four registers for temporarily storing computational data. The storage registers are made to have different sizes for storing different sized packets of computational data.

Claims

1. A baseband controller system, comprising:

a plurality of buses coupled to communicate with a plurality of hardware blocks;

a microsequencer also coupled to the plurality of buses;

the microsequencer comprising a 72-bit correlator/accumulator; and

transceiver circuitry coupled to at least one of the plurality of buses.

2. The baseband controller system of claim 1 wherein the microsequencer further comprises a 72-bit arithmetic logic unit.

3. The baseband controller system of claim 1 wherein the microsequencer further comprises a plurality of temporary registers for storing computational data.

4. The baseband controller system of claim 3 wherein the temporary registers include a 64-bit register.

5. The baseband controller system of claim 3 wherein the temporary registers include a 48-bit register.

6. The baseband controller system of claim 3 wherein the temporary registers include a 32-bit register.

7. The baseband controller system of claim 3 wherein the temporary registers include a 16-bit register.

8. The baseband controller system of claim 3 wherein the temporary registers include a 64-bit register, a 48-bit register, a 32-bit register and a 16-bit register.

9. The baseband controller system of claim 8 further including logic circuitry to determine which temporary register should be used to store a piece of computational data based upon the size of the piece of computational data.

10. The baseband controller system of claim 1 wherein the microsequencer comprises a plurality of clocks, including a native Bluetooth clock.

11. The baseband controller system of claim 1 wherein the microsequencer comprises a plurality of clocks, including a native real-time clock.

12. The baseband controller system of claim 1 wherein the microsequencer comprises a plurality of clocks, including an externally driven Bluetooth clock.

13. The baseband controller system of claim 1 wherein the microsequencer comprises a plurality of clocks, including an externally driven real-time clock.

14. The baseband controller system of claim 1 wherein the microsequencer comprises a plurality of timers.

15. The baseband controller system of claim 1 wherein the microsequencer comprises a plurality of timers wherein the plurality of timers comprises at least four timers.

16. The baseband controller system of claim 1 wherein the microsequencer includes eight timers.

17. A microsequencer for use as a real-time Bluetooth baseband controller, comprising:

timer circuitry;

temporary data storage circuitry; and

a plurality of Bluetooth and native clocks for supporting timing functionality according to Bluetooth specifications.

18. The microsequencer of claim 17 wherein the plurality of native and externally driven clocks include an externally driven Bluetooth clock.

19. The microsequencer of claim 17 wherein the plurality of native and externally driven clocks include a native Bluetooth clock.

20. The microsequencer of claim 17 wherein the plurality of native and externally driven clocks include an external real-time clock.

21. The microsequencer of claim 17 wherein the plurality of native and externally driven clocks include a native real-time clock.

22. The microsequencer of claim 17 wherein the temporary data storage circuitry includes a 64-bit storage register.

23. The microsequencer of claim 17 wherein the temporary data storage circuitry includes a 48-bit storage register.

24. The microsequencer of claim 17 wherein the temporary data storage circuitry includes a 32-bit storage register.

25. The microsequencer of claim 17 wherein the temporary data storage circuitry includes a 16-bit storage register.

26. The microsequencer of claim 17 wherein the temporary data storage circuitry includes a 64-bit register, a 48-bit register, a 32-bit register and a 16-bit register.

27. The microsequencer of claim 17 wherein the temporary data storage circuitry includes registers of different size and further wherein the microsequencer includes a data storage logic module, which data storage logic module determines which available register should be used for storing data based upon the size of the data that is to be temporarily stored.

28. The microsequencer of claim 17 wherein the timers include at least four timers.

29. The micro-sequencer of claim 17 wherein the timers include at least eight timers.

30. The micro-sequencer of claim 27 further including timer control logic circuitry for controlling the operation of the at least eight timers.

31. A microsequencer for use as a real-time Bluetooth baseband controller, comprising:

eight timers to provide traditional timer functionality;

timer control logic circuitry;

an externally driven Bluetooth clock;

an externally driven real-time clock;

a native Bluetooth clock;

a native real-time clock;

a 64-bit register for temporarily storing computational data;

a 48-bit storage register for temporarily storing computational data;

a 32-bit storage register for temporarily storing computational data;

a 16-bit storage register for temporarily storing computational data; and

data storage logic circuitry for determining which of the temporary storage registers is to store a piece of data that is to be temporarily stored.

32. The microsequencer of claim 31 wherein the period of one Bluetooth clock cycle is equal to 312.5 real-time clock cycle periods.