Method and apparatus for integration of communication links with a remote direct memory access protocol

• US 20030097518A1
• Filed: 10/16/2002
• Published: 05/22/2003
• Est. Priority Date: 10/22/2001
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: K. Wong, Michael, Kohn, Leslie D.
• Granted Patent: US 6,901,491 B2
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 3/1423 controlling a plurality of local displays, e.g. CRT and flat panel display
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: G09G 2352/00 Parallel handling of streams of display data
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2370/022 Centralised management of display operation, e.g. in a server instead of locally
• CPC Class Codes: G09G 2370/20 Details of the management of multiple sources of image data
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: H04L 45/745 : Address table lookup; Address filtering
• CPC Class Codes: H04L 47/10 : Flow control; Congestion control
• CPC Class Codes: H04L 47/2441 : relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/9057 : Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9089 : replacing packets in a storage arrangement, e.g. pushout
• CPC Class Codes: H04L 69/22 : Parsing or analysis of headers
• CPC Class Codes: H04L 9/40 : Network security protocols
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, a server is provided. The server includes multiple application processor chips. Each of the multiple application processor chips includes multiple processing cores. Multiple memories corresponding to the multiple processor chips are included. The multiple memories are configured such that one processor chip is associated with one memory. A plurality of fabric chips enabling each of the multiple application processor chips to access any of the multiple memories are included. The data associated with one of the multiple application processor chips is stored across each of the multiple memories. In one embodiment, the application processor chips include a remote direct memory access (RDMA) and striping engine. The RDMA and striping engine is configured to store data in a striped manner across the multiple memories. A method for allowing multiple processors to exchange information through horizontal scaling is also provided.

Claims

1. A server, comprising:

multiple application processor chips, each of the multiple application processor chips having multiple processing cores;

multiple memories corresponding to the multiple processor chips such that one processor chip is associated with one memory; and

a plurality of fabric chips enabling each of the multiple application processor chips to access any of the multiple memories, wherein data associated with one of the multiple application processor chips is stored across each of the multiple memories.

2. The server of claim 1, wherein each of the multiple processor chips include,

a remote direct memory access (RDMA) and striping engine, the RDMA and striping engine configured to store data in a striped manner across the multiple memories.

3. The server of claim 1, wherein one of the multiple memories functions as a parity block for data recovery.

4. The server of claim 1, wherein a number of application processor chips is equal to four, a number of processing cores on each application processing chip is equal to 8, and a number of fabric chips is equal to 16.

5. The server of claim 3, wherein the data in the parity block is recreated through an exclusive or operation.

6. The server of claim 1 wherein the multiple memories are dynamic random access memories.

7. The server of claim 1, wherein the processing cores are based on Scalable Processor Architecture

8. The server of claim 3, wherein a failure model of n+1 for the application processor chips is achieved through the parity block.

9. A method for allowing multiple processors to exchange information through horizontal scaling, comprising:

providing multiple processor chips having multiple processing cores, each of the multiple processor chips associated with a memory, such that one processor chip is associated with one memory;

enabling each of the multiple processor chips to communicate with each other;

identifying a block of data to be stored in memory;

subdividing the block of data into segments; and

interleaving the segments across each memory associated with each processor chip.

10. The method of claim 9, wherein the method operation of interleaving the segments across each memory associated with each processor chip includes,

parity striping the segments to allow for data recovery.

11. The method of claim 9, wherein the method operation of enabling each of the multiple processor chips to communicate with each other includes,

linking each of the multiple processor chips with a plurality of fabric chips.

12. The method of claim 11, wherein transaction requests can be independently sent out through the plurality of fabric chips.

13. The method of claim 11, wherein a remote direct memory access protocol is implemented through communication links between the multiple processor chips.

14. The method of claim 9, wherein the method operation of interleaving the segments across each memory associated with each processor chip alleviates hot spot contention.

15. The method of claim 9, further including:

detecting an error when accessing data from one of the multiple memories, the error rendering the data unavailable; and

recreating the unavailable data from an other one of the multiple memories.

16. The method of claim 15, wherein the method operation of recreating the unavailable data from an other one of the multiple memories includes,

accessing the other one of the multiple memories;

performing an exclusive or operation on data within the recreating the unavailable data from an other one of the multiple memories; and

recovering the unavailable data.

17. The method of claim 15, wherein the other one of the multiple memories functions as a parity block.

18. The method of claim 9, wherein the multiple memories are dynamic random access memories.

19. The method of claim 9, wherein the multiple processors are configured to execute a server application.