High-speed first-in-first-out buffer

• US 20030097526A1
• Filed: 11/19/2001
• Published: 05/22/2003
• Est. Priority Date: 11/19/2001
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Das, Debaleena, Chiu, Kenneth Y., McMahon, Daniel F., Schulz, Jurgen M.
• Granted Patent: US 6,802,036 B2
• Time in Patent Office: Days
• US Class Current: 711/117
• CPC Class Codes: G06F 5/08 having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register G06F5/065 takes precedence; shift registers per se G11C19/00
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence

Abstract

A buffer, having a first buffer input, a second buffer input, and a buffer output. The buffer is configured to store a plurality of data entries. The buffer includes: a first memory, the first memory having an input and an output. The input of the first memory is coupled to the first buffer input. The buffer also includes a second memory. The second memory has an input and an output. The input of the second memory is coupled to the second buffer input. The buffer also includes a first register. The first register has an input and an output. The input of the first register is coupled to the first buffer input, the second buffer input, the output of the first memory, and the output of the second memory. The output of the first register is coupled to the buffer output. The buffer also includes a second register configured to store a second data entry. The second register has an input and an output. The input of the second register is coupled to the first buffer input, the second buffer input, the output of the first memory, and the output of the second memory. The output of the second register is coupled to the input of the first register.

Claims

1. A buffer, having a first buffer input, a second buffer input, and a buffer output, the buffer configured to store a plurality of data entries, the buffer comprising:

a) a first memory, the first memory having an input and an output, the input of the first memory being coupled to the first buffer input;

b) a second memory, the second memory having an input and an output, the input of the second memory being coupled to the second buffer input;

c) a first register, the first register having an input and an output, the input of the first register being coupled to the first buffer input, the second buffer input, the output of the first memory, and the output of the second memory, the output of the first register being coupled to the buffer output; and

d) a second register configured to store a second data entry, the second register having an input and an output, the input of the second register being coupled to the first buffer input, the second buffer input, the output of the first memory, and the output of the second memory, the output of the second register being coupled to the input of the first register.

2. The buffer of claim 1 further comprising:

e) a third register, the third register having an input and an output, the input of the third register being coupled to the first buffer input, the second buffer input, the output of the first memory, and the output of the second memory, the output of the third register being coupled to the input of the second register.

3. The buffer of claim 1 further comprising:

e) control logic coupled to the first memory, the second memory, the first register, and the second register.

4. The buffer of claim 3, wherein the control logic includes diagnostic circuitry.

5. The buffer of claim 1, wherein the first buffer input is coupled to the first memory by a multiplexer.

6. The buffer of claim 1, wherein the first register is coupled to the first buffer input by a multiplexer.

7. The buffer of claim 1, wherein the first register is coupled to the output of the first memory by a multiplexer.

22. The buffer of claim 1, wherein the first buffer input is coupled to the first memory by a register and a multiplexer.

8. A buffer, having a first buffer input, a second buffer input, and a buffer output, the buffer configured to store a plurality of data entries, the buffer comprising:

a) a first error generation code circuit having an input and an output, the input of the first error generation code circuit being coupled to the first buffer input;

b) a first memory, the first memory having an input and an output, the input of the first memory being coupled to the output of the first error generation code circuit;

c) a first error code detection and correction circuit having an input and an output, the input of the first error code detection and correction circuit coupled to the output of the first memory;

d) a second error generation code circuit having an input and an output, the input of the second error generation code circuit being coupled to the second buffer input;

e) a second memory, the second memory having an input and an output, the input of the second memory being coupled the output of the second error generation code circuit;

f) a second error code detection and correction circuit having an input and an output, the input of the second error code detection and correction circuit coupled to the output of the second memory;

g) a first register, the first register having an input and an output, the input of the first register being coupled to the first buffer input, the second buffer input, the output of the first error code detection and correction circuit, and the output of the second error code detection and correction circuit, the output of the first register being coupled to the buffer output; and

h) a second register configured to store a second data entry, the second register having an input and an output, the input of the second register being coupled to the first buffer input, the second buffer input, the output of the first error code detection and correction circuit, and the output of the second error code detection and correction circuit, the output of the second register being coupled to the input of the first register.

9. The buffer of claim 8 further comprising:

i) a third register, the third register having an input and an output, the input of the third register being coupled to the first buffer input, the second buffer input, the output of the first error code detection and correction circuit, and the output of the second error code detection and correction circuit, the output of the third register being coupled to the input of the second register.

10. The buffer of claim 8 further comprising:

i) control logic coupled to the first memory, the second memory, the first register, and the second register.

11. The buffer of claim 10, wherein the control logic includes diagnostic circuitry.

12. The buffer of claim 8, wherein the first buffer input is coupled to the first error code generation circuit by a multiplexer.

13. The buffer of claim 8, wherein the first register is coupled to the first buffer input by a multiplexer.

14. The buffer of claim 8, wherein first register is coupled to the output of the first error code detection and correction circuit by a multiplexer.

23. The buffer of claim 8, wherein the first buffer input is coupled to the first error generation code circuit by a register and a multiplexer.

15. A buffer, having a buffer input and a buffer output, the buffer configured to store a plurality of data entries, the buffer comprising:

a) an error generation code circuit having an input and an output, the input of the error generation code circuit being coupled to the buffer input;

b) a memory, the memory having an input and an output, the input of the memory being coupled to the output of the error generation code circuit;

c) an error code detection and correction circuit having an input and an output, the input of the error code detection and correction circuit coupled to the output of the memory; and

d) a first register, the first register having an input and an output, the input of the first register being coupled to the buffer input, and the output of the error code detection and correction circuit, the output of the first register being coupled to the buffer output.

16. The buffer of claim 15, further comprising:

e) a second register, the second register having an input and an output, the input of the second register being coupled to the buffer input, and the output of the error code detection and correction circuit, the output of the second register being coupled to the input of the first register.

17. The buffer of claim 15, further comprising:

e) control logic coupled to the memory and the first register.

18. The buffer of claim 17, wherein the control logic includes diagnostic circuitry.

19. The buffer of claim 15, wherein the buffer input is coupled to the error code generation circuit by a multiplexer.

20. The buffer of claim 15, wherein the first register is coupled to the buffer input by a multiplexer.

21. The buffer of claim 15, wherein first register is coupled to the output of the error code detection and correction circuit by a multiplexer.

24. The buffer of claim 15, wherein the first buffer input is coupled to the first error generation code circuit by a register and a multiplexer.